1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/jcore,pit.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: J-Core Programmable Interval Timer and Clocksource
8
9maintainers:
10  - Rich Felker <dalias@libc.org>
11
12properties:
13  compatible:
14    const: jcore,pit
15
16  reg:
17    description:
18      Memory region(s) for timer/clocksource registers. For SMP, there should be
19      one region per cpu, indexed by the sequential, zero-based hardware cpu
20      number.
21
22  interrupts:
23    description:
24      An interrupt to assign for the timer. The actual pit core is integrated
25      with the aic and allows the timer interrupt assignment to be programmed by
26      software, but this property is required in order to reserve an interrupt
27      number that doesn't conflict with other devices.
28    maxItems: 1
29
30required:
31  - compatible
32  - reg
33  - interrupts
34
35additionalProperties: false
36
37examples:
38  - |
39    timer@200 {
40        compatible = "jcore,pit";
41        reg = <0x200 0x30 0x500 0x30>;
42        interrupts = <0x48>;
43    };
44