1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Cadence NAND flash controller driver 4 * 5 * Copyright (C) 2019 Cadence 6 * 7 * Author: Piotr Sroka <piotrs@cadence.com> 8 * 9 */ 10 11 #ifndef _CADENCE_NAND_H_ 12 #define _CADENCE_NAND_H_ 13 #include <clk.h> 14 #include <reset.h> 15 #include <linux/types.h> 16 #include <linux/mtd/rawnand.h> 17 18 /* 19 * HPNFC can work in 3 modes: 20 * - PIO - can work in master or slave DMA 21 * - CDMA - needs Master DMA for accessing command descriptors. 22 * - Generic mode - can use only slave DMA. 23 * CDMA and PIO modes can be used to execute only base commands. 24 * CDMA and PIO modes can be used to execute only base commands. 25 * Generic mode can be used to execute any command 26 * on NAND flash memory. Driver uses CDMA mode for 27 * block erasing, page reading, page programing. 28 * Generic mode is used for executing rest of commands. 29 */ 30 31 #define DMA_DATA_SIZE_ALIGN 8 32 33 /* Register definition. */ 34 /* 35 * Command register 0. 36 * Writing data to this register will initiate a new transaction 37 * of the NF controller. 38 */ 39 #define CMD_REG0 0x0000 40 /* Command type field mask. */ 41 #define CMD_REG0_CT GENMASK(31, 30) 42 /* Command type CDMA. */ 43 #define CMD_REG0_CT_CDMA 0uL 44 /* Command type generic. */ 45 #define CMD_REG0_CT_GEN 3uL 46 /* Command thread number field mask. */ 47 #define CMD_REG0_TN GENMASK(27, 24) 48 49 /* Command register 2. */ 50 #define CMD_REG2 0x0008 51 /* Command register 3. */ 52 #define CMD_REG3 0x000C 53 /* Pointer register to select which thread status will be selected. */ 54 #define CMD_STATUS_PTR 0x0010 55 /* Command status register for selected thread. */ 56 #define CMD_STATUS 0x0014 57 58 /* Interrupt status register. */ 59 #define INTR_STATUS 0x0110 60 #define INTR_STATUS_SDMA_ERR BIT(22) 61 #define INTR_STATUS_SDMA_TRIGG BIT(21) 62 #define INTR_STATUS_UNSUPP_CMD BIT(19) 63 #define INTR_STATUS_DDMA_TERR BIT(18) 64 #define INTR_STATUS_CDMA_TERR BIT(17) 65 #define INTR_STATUS_CDMA_IDL BIT(16) 66 67 /* Interrupt enable register. */ 68 #define INTR_ENABLE 0x0114 69 #define INTR_ENABLE_INTR_EN BIT(31) 70 71 /* Controller internal state. */ 72 #define CTRL_STATUS 0x0118 73 #define CTRL_STATUS_INIT_COMP BIT(9) 74 #define CTRL_STATUS_CTRL_BUSY BIT(8) 75 76 /* Command Engine threads state. */ 77 #define TRD_STATUS 0x0120 78 79 /* Command Engine interrupt thread error status. */ 80 #define TRD_ERR_INT_STATUS 0x0128 81 /* Command Engine interrupt thread error enable. */ 82 #define TRD_ERR_INT_STATUS_EN 0x0130 83 /* Command Engine interrupt thread complete status. */ 84 #define TRD_COMP_INT_STATUS 0x0138 85 86 /* 87 * Transfer config 0 register. 88 * Configures data transfer parameters. 89 */ 90 #define TRAN_CFG_0 0x0400 91 /* Offset value from the beginning of the page. */ 92 #define TRAN_CFG_0_OFFSET GENMASK(31, 16) 93 /* Numbers of sectors to transfer within singlNF device's page. */ 94 #define TRAN_CFG_0_SEC_CNT GENMASK(7, 0) 95 96 /* 97 * Transfer config 1 register. 98 * Configures data transfer parameters. 99 */ 100 #define TRAN_CFG_1 0x0404 101 /* Size of last data sector. */ 102 #define TRAN_CFG_1_LAST_SEC_SIZE GENMASK(31, 16) 103 /* Size of not-last data sector. */ 104 #define TRAN_CFG_1_SECTOR_SIZE GENMASK(15, 0) 105 106 /* ECC engine configuration register 0. */ 107 #define ECC_CONFIG_0 0x0428 108 /* Correction strength. */ 109 #define ECC_CONFIG_0_CORR_STR GENMASK(10, 8) 110 /* Enable erased pages detection mechanism. */ 111 #define ECC_CONFIG_0_ERASE_DET_EN BIT(1) 112 /* Enable controller ECC check bits generation and correction. */ 113 #define ECC_CONFIG_0_ECC_EN BIT(0) 114 115 /* ECC engine configuration register 1. */ 116 #define ECC_CONFIG_1 0x042C 117 118 /* Multiplane settings register. */ 119 #define MULTIPLANE_CFG 0x0434 120 /* Cache operation settings. */ 121 #define CACHE_CFG 0x0438 122 123 /* Transferred data block size for the slave DMA module. */ 124 #define SDMA_SIZE 0x0440 125 126 /* Thread number associated with transferred data block 127 * for the slave DMA module. 128 */ 129 #define SDMA_TRD_NUM 0x0444 130 /* Thread number mask. */ 131 #define SDMA_TRD_NUM_SDMA_TRD GENMASK(2, 0) 132 133 #define CONTROL_DATA_CTRL 0x0494 134 /* Thread number mask. */ 135 #define CONTROL_DATA_CTRL_SIZE GENMASK(15, 0) 136 137 #define CTRL_VERSION 0x800 138 #define CTRL_VERSION_REV GENMASK(7, 0) 139 140 /* Available hardware features of the controller. */ 141 #define CTRL_FEATURES 0x804 142 /* Support for NV-DDR2/3 work mode. */ 143 #define CTRL_FEATURES_NVDDR_2_3 BIT(28) 144 /* Support for NV-DDR work mode. */ 145 #define CTRL_FEATURES_NVDDR BIT(27) 146 /* Support for asynchronous work mode. */ 147 #define CTRL_FEATURES_ASYNC BIT(26) 148 /* Support for asynchronous work mode. */ 149 #define CTRL_FEATURES_N_BANKS GENMASK(25, 24) 150 /* Slave and Master DMA data width. */ 151 #define CTRL_FEATURES_DMA_DWITH64 BIT(21) 152 /* Availability of Control Data feature.*/ 153 #define CTRL_FEATURES_CONTROL_DATA BIT(10) 154 155 /* BCH Engine identification register 0 - correction strengths. */ 156 #define BCH_CFG_0 0x838 157 #define BCH_CFG_0_CORR_CAP_0 GENMASK(7, 0) 158 #define BCH_CFG_0_CORR_CAP_1 GENMASK(15, 8) 159 #define BCH_CFG_0_CORR_CAP_2 GENMASK(23, 16) 160 #define BCH_CFG_0_CORR_CAP_3 GENMASK(31, 24) 161 162 /* BCH Engine identification register 1 - correction strengths. */ 163 #define BCH_CFG_1 0x83C 164 #define BCH_CFG_1_CORR_CAP_4 GENMASK(7, 0) 165 #define BCH_CFG_1_CORR_CAP_5 GENMASK(15, 8) 166 #define BCH_CFG_1_CORR_CAP_6 GENMASK(23, 16) 167 #define BCH_CFG_1_CORR_CAP_7 GENMASK(31, 24) 168 169 /* BCH Engine identification register 2 - sector sizes. */ 170 #define BCH_CFG_2 0x840 171 #define BCH_CFG_2_SECT_0 GENMASK(15, 0) 172 #define BCH_CFG_2_SECT_1 GENMASK(31, 16) 173 174 /* BCH Engine identification register 3. */ 175 #define BCH_CFG_3 0x844 176 #define BCH_CFG_3_METADATA_SIZE GENMASK(23, 16) 177 178 /* Ready/Busy# line status. */ 179 #define RBN_SETINGS 0x1004 180 181 /* Common settings. */ 182 #define COMMON_SET 0x1008 183 /* 16 bit device connected to the NAND Flash interface. */ 184 #define COMMON_SET_DEVICE_16BIT BIT(8) 185 186 /* Skip_bytes registers. */ 187 #define SKIP_BYTES_CONF 0x100C 188 #define SKIP_BYTES_MARKER_VALUE GENMASK(31, 16) 189 #define SKIP_BYTES_NUM_OF_BYTES GENMASK(7, 0) 190 191 #define SKIP_BYTES_OFFSET 0x1010 192 #define SKIP_BYTES_OFFSET_VALUE GENMASK(23, 0) 193 194 /* Timings configuration. */ 195 #define ASYNC_TOGGLE_TIMINGS 0x101c 196 #define ASYNC_TOGGLE_TIMINGS_TRH GENMASK(28, 24) 197 #define ASYNC_TOGGLE_TIMINGS_TRP GENMASK(20, 16) 198 #define ASYNC_TOGGLE_TIMINGS_TWH GENMASK(12, 8) 199 #define ASYNC_TOGGLE_TIMINGS_TWP GENMASK(4, 0) 200 201 #define TIMINGS0 0x1024 202 #define TIMINGS0_TADL GENMASK(31, 24) 203 #define TIMINGS0_TCCS GENMASK(23, 16) 204 #define TIMINGS0_TWHR GENMASK(15, 8) 205 #define TIMINGS0_TRHW GENMASK(7, 0) 206 207 #define TIMINGS1 0x1028 208 #define TIMINGS1_TRHZ GENMASK(31, 24) 209 #define TIMINGS1_TWB GENMASK(23, 16) 210 #define TIMINGS1_TVDLY GENMASK(7, 0) 211 212 #define TIMINGS2 0x102c 213 #define TIMINGS2_TFEAT GENMASK(25, 16) 214 #define TIMINGS2_CS_HOLD_TIME GENMASK(13, 8) 215 #define TIMINGS2_CS_SETUP_TIME GENMASK(5, 0) 216 217 /* Configuration of the resynchronization of slave DLL of PHY. */ 218 #define DLL_PHY_CTRL 0x1034 219 #define DLL_PHY_CTRL_DLL_RST_N BIT(24) 220 #define DLL_PHY_CTRL_EXTENDED_WR_MODE BIT(17) 221 #define DLL_PHY_CTRL_EXTENDED_RD_MODE BIT(16) 222 #define DLL_PHY_CTRL_RS_HIGH_WAIT_CNT GENMASK(11, 8) 223 #define DLL_PHY_CTRL_RS_IDLE_CNT GENMASK(7, 0) 224 225 /* TODO: - Identify better way to handle PHY address */ 226 #define PHY_OFFSET 0x10000 227 228 /* Register controlling DQ related timing. */ 229 #define PHY_DQ_TIMING PHY_OFFSET + 0x2000 230 /* Register controlling DSQ related timing. */ 231 #define PHY_DQS_TIMING PHY_OFFSET + 0x2004 232 #define PHY_DQS_TIMING_DQS_SEL_OE_END GENMASK(3, 0) 233 #define PHY_DQS_TIMING_PHONY_DQS_SEL BIT(16) 234 #define PHY_DQS_TIMING_USE_PHONY_DQS BIT(20) 235 236 /* Register controlling the gate and loopback control related timing. */ 237 #define PHY_GATE_LPBK_CTRL PHY_OFFSET + 0x2008 238 #define PHY_GATE_LPBK_CTRL_RDS GENMASK(24, 19) 239 240 /* Register holds the control for the master DLL logic. */ 241 #define PHY_DLL_MASTER_CTRL PHY_OFFSET + 0x200C 242 #define PHY_DLL_MASTER_CTRL_BYPASS_MODE BIT(23) 243 244 /* Register holds the control for the slave DLL logic. */ 245 #define PHY_DLL_SLAVE_CTRL PHY_OFFSET + 0x2010 246 247 /* This register handles the global control settings for the PHY. */ 248 #define PHY_CTRL PHY_OFFSET + 0x2080 249 #define PHY_CTRL_SDR_DQS BIT(14) 250 #define PHY_CTRL_PHONY_DQS GENMASK(9, 4) 251 252 /* 253 * This register handles the global control settings 254 * for the termination selects for reads. 255 */ 256 #define PHY_TSEL PHY_OFFSET + 0x2084 257 258 /* Generic command layout. */ 259 #define GCMD_LAY_CS GENMASK_ULL(11, 8) 260 /* 261 * This bit informs the minicotroller if it has to wait for tWB 262 * after sending the last CMD/ADDR/DATA in the sequence. 263 */ 264 #define GCMD_LAY_TWB BIT_ULL(6) 265 /* Type of generic instruction. */ 266 #define GCMD_LAY_INSTR GENMASK_ULL(5, 0) 267 268 /* Generic CMD sequence type. */ 269 #define GCMD_LAY_INSTR_CMD 0 270 /* Generic ADDR sequence type. */ 271 #define GCMD_LAY_INSTR_ADDR 1 272 /* Generic data transfer sequence type. */ 273 #define GCMD_LAY_INSTR_DATA 2 274 275 /* Input part of generic command type of input is command. */ 276 #define GCMD_LAY_INPUT_CMD GENMASK_ULL(23, 16) 277 278 /* Generic command address sequence - address fields. */ 279 #define GCMD_LAY_INPUT_ADDR GENMASK_ULL(63, 16) 280 /* Generic command address sequence - address size. */ 281 #define GCMD_LAY_INPUT_ADDR_SIZE GENMASK_ULL(13, 11) 282 283 /* Transfer direction field of generic command data sequence. */ 284 #define GCMD_DIR BIT_ULL(11) 285 /* Read transfer direction of generic command data sequence. */ 286 #define GCMD_DIR_READ 0 287 /* Write transfer direction of generic command data sequence. */ 288 #define GCMD_DIR_WRITE 1 289 290 /* ECC enabled flag of generic command data sequence - ECC enabled. */ 291 #define GCMD_ECC_EN BIT_ULL(12) 292 /* Generic command data sequence - sector size. */ 293 #define GCMD_SECT_SIZE GENMASK_ULL(31, 16) 294 /* Generic command data sequence - sector count. */ 295 #define GCMD_SECT_CNT GENMASK_ULL(39, 32) 296 /* Generic command data sequence - last sector size. */ 297 #define GCMD_LAST_SIZE GENMASK_ULL(55, 40) 298 299 /* CDMA descriptor fields. */ 300 /* Erase command type of CDMA descriptor. */ 301 #define CDMA_CT_ERASE 0x1000 302 /* Program page command type of CDMA descriptor. */ 303 #define CDMA_CT_WR 0x2100 304 /* Read page command type of CDMA descriptor. */ 305 #define CDMA_CT_RD 0x2200 306 307 /* Flash pointer memory shift. */ 308 #define CDMA_CFPTR_MEM_SHIFT 24 309 /* Flash pointer memory mask. */ 310 #define CDMA_CFPTR_MEM GENMASK(26, 24) 311 312 /* 313 * Command DMA descriptor flags. If set causes issue interrupt after 314 * the completion of descriptor processing. 315 */ 316 #define CDMA_CF_INT BIT(8) 317 /* 318 * Command DMA descriptor flags - the next descriptor 319 * address field is valid and descriptor processing should continue. 320 */ 321 #define CDMA_CF_CONT BIT(9) 322 /* DMA master flag of command DMA descriptor. */ 323 #define CDMA_CF_DMA_MASTER BIT(10) 324 325 /* Operation complete status of command descriptor. */ 326 #define CDMA_CS_COMP BIT(15) 327 /* Operation complete status of command descriptor. */ 328 /* Command descriptor status - operation fail. */ 329 #define CDMA_CS_FAIL BIT(14) 330 /* Command descriptor status - page erased. */ 331 #define CDMA_CS_ERP BIT(11) 332 /* Command descriptor status - timeout occurred. */ 333 #define CDMA_CS_TOUT BIT(10) 334 /* 335 * Maximum amount of correction applied to one ECC sector. 336 * It is part of command descriptor status. 337 */ 338 #define CDMA_CS_MAXERR GENMASK(9, 2) 339 /* Command descriptor status - uncorrectable ECC error. */ 340 #define CDMA_CS_UNCE BIT(1) 341 /* Command descriptor status - descriptor error. */ 342 #define CDMA_CS_ERR BIT(0) 343 344 /* Status of operation - OK. */ 345 #define STAT_OK 0 346 /* Status of operation - FAIL. */ 347 #define STAT_FAIL 2 348 /* Status of operation - uncorrectable ECC error. */ 349 #define STAT_ECC_UNCORR 3 350 /* Status of operation - page erased. */ 351 #define STAT_ERASED 5 352 /* Status of operation - correctable ECC error. */ 353 #define STAT_ECC_CORR 6 354 /* Status of operation - unsuspected state. */ 355 #define STAT_UNKNOWN 7 356 /* Status of operation - operation is not completed yet. */ 357 #define STAT_BUSY 0xFF 358 359 #define BCH_MAX_NUM_CORR_CAPS 8 360 #define BCH_MAX_NUM_SECTOR_SIZES 2 361 362 #define ONE_CYCLE 1 363 #define TIMEOUT_US 1000000 364 365 struct cadence_nand_timings { 366 u32 async_toggle_timings; 367 u32 timings0; 368 u32 timings1; 369 u32 timings2; 370 u32 dll_phy_ctrl; 371 u32 phy_ctrl; 372 u32 phy_dqs_timing; 373 u32 phy_gate_lpbk_ctrl; 374 }; 375 376 /* Command DMA descriptor. */ 377 struct cadence_nand_cdma_desc { 378 /* Next descriptor address. */ 379 u64 next_pointer; 380 381 /* Flash address is a 32-bit address comprising of BANK and ROW ADDR. */ 382 u32 flash_pointer; 383 /*field appears in HPNFC version 13*/ 384 u16 bank; 385 u16 rsvd0; 386 387 /* Operation the controller needs to perform. */ 388 u16 command_type; 389 u16 rsvd1; 390 /* Flags for operation of this command. */ 391 u16 command_flags; 392 u16 rsvd2; 393 394 /* System/host memory address required for data DMA commands. */ 395 u64 memory_pointer; 396 397 /* Status of operation. */ 398 u32 status; 399 u32 rsvd3; 400 401 /* Address pointer to sync buffer location. */ 402 u64 sync_flag_pointer; 403 404 /* Controls the buffer sync mechanism. */ 405 u32 sync_arguments; 406 u32 rsvd4; 407 408 /* Control data pointer. */ 409 u64 ctrl_data_ptr; 410 }; 411 412 /* Interrupt status. */ 413 struct cadence_nand_irq_status { 414 /* Thread operation complete status. */ 415 u32 trd_status; 416 /* Thread operation error. */ 417 u32 trd_error; 418 /* Controller status. */ 419 u32 status; 420 }; 421 422 /* Cadence NAND flash controller capabilities get from driver data. */ 423 struct cadence_nand_dt_devdata { 424 /* Skew value of the output signals of the NAND Flash interface. */ 425 u32 if_skew; 426 /* It informs if slave DMA interface is connected to DMA engine. */ 427 unsigned int has_dma:1; 428 }; 429 430 /* Cadence NAND flash controller capabilities read from registers. */ 431 struct cdns_nand_caps { 432 /* Maximum number of banks supported by hardware. */ 433 u8 max_banks; 434 /* Slave and Master DMA data width in bytes (4 or 8). */ 435 u8 data_dma_width; 436 /* Control Data feature supported. */ 437 bool data_control_supp; 438 /* Is PHY type DLL. */ 439 bool is_phy_type_dll; 440 }; 441 442 struct cadence_nand_info { 443 struct nand_hw_control controller; 444 struct udevice *dev; 445 struct reset_ctl softphy_reset; 446 struct reset_ctl nand_reset; 447 struct cadence_nand_cdma_desc *cdma_desc; 448 /* IP capability. */ 449 const struct cadence_nand_dt_devdata *caps1; 450 struct cdns_nand_caps caps2; 451 u8 ctrl_rev; 452 dma_addr_t dma_cdma_desc; 453 /* command interface buffers */ 454 u8 *buf; 455 u32 buf_size; 456 u8 *stat; 457 u8 cmd; 458 u32 buf_index; 459 460 u8 curr_corr_str_idx; 461 462 /* Register interface. */ 463 void __iomem *reg; 464 465 struct { 466 void __iomem *virt; 467 dma_addr_t dma; 468 } io; 469 470 int irq; 471 /* Interrupts that have happened. */ 472 struct cadence_nand_irq_status irq_status; 473 /* Interrupts we are waiting for. */ 474 struct cadence_nand_irq_status irq_mask; 475 476 int ecc_strengths[BCH_MAX_NUM_CORR_CAPS]; 477 struct nand_ecc_step_info ecc_stepinfos[BCH_MAX_NUM_SECTOR_SIZES]; 478 struct nand_ecc_caps ecc_caps; 479 480 int curr_trans_type; 481 482 struct clk clk; 483 u32 nf_clk_rate; 484 /* 485 * Estimated Board delay. The value includes the total 486 * round trip delay for the signals and is used for deciding on values 487 * associated with data read capture. 488 */ 489 u32 board_delay; 490 491 struct nand_chip *selected_chip; 492 493 unsigned long assigned_cs; 494 struct list_head chips; 495 u8 bch_metadata_size; 496 }; 497 498 struct cdns_nand_chip { 499 struct cadence_nand_timings timings; 500 struct nand_chip chip; 501 u8 nsels; 502 struct list_head node; 503 504 /* 505 * part of oob area of NAND flash memory page. 506 * This part is available for user to read or write. 507 */ 508 u32 avail_oob_size; 509 510 /* Sector size. There are few sectors per mtd->writesize */ 511 u32 sector_size; 512 u32 sector_count; 513 514 /* Offset of BBM. */ 515 u8 bbm_offs; 516 /* Number of bytes reserved for BBM. */ 517 u8 bbm_len; 518 /* ECC strength index. */ 519 u8 corr_str_idx; 520 521 u8 cs[]; 522 }; 523 524 struct ecc_info { 525 int (*calc_ecc_bytes)(int step_size, int strength); 526 int max_step_size; 527 }; 528 529 #endif /*_CADENCE_NAND_H_*/ 530