1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * Hayden Fraser (Hayden.Fraser@freescale.com) 4 */ 5 6 #ifndef _M5253DEMO_H 7 #define _M5253DEMO_H 8 9 #include <linux/stringify.h> 10 11 #define CFG_SYS_UART_PORT (0) 12 13 /* Configuration for environment 14 * Environment is embedded in u-boot in the second sector of the flash 15 */ 16 17 #define LDS_BOARD_TEXT \ 18 . = DEFINED(env_offset) ? env_offset : .; \ 19 env/embedded.o(.text*); 20 21 #ifdef CONFIG_DRIVER_DM9000 22 # define CFG_EXTRA_ENV_SETTINGS \ 23 "netdev=eth0\0" \ 24 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 25 "loadaddr=10000\0" \ 26 "u-boot=u-boot.bin\0" \ 27 "load=tftp ${loadaddr) ${u-boot}\0" \ 28 "upd=run load; run prog\0" \ 29 "prog=prot off 0xff800000 0xff82ffff;" \ 30 "era 0xff800000 0xff82ffff;" \ 31 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 32 "save\0" \ 33 "" 34 #endif 35 36 /* I2C */ 37 #define CFG_SYS_I2C_PINMUX_REG (*(u32 *) (CFG_SYS_MBAR+0x19C)) 38 #define CFG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 39 #define CFG_SYS_I2C_PINMUX_SET (0) 40 41 #undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 42 #define CFG_SYS_FAST_CLK 43 #ifdef CFG_SYS_FAST_CLK 44 # define CFG_SYS_PLLCR 0x1243E054 45 # define CFG_SYS_CLK 140000000 46 #else 47 # define CFG_SYS_PLLCR 0x135a4140 48 # define CFG_SYS_CLK 70000000 49 #endif 50 51 /* 52 * Low Level Configuration Settings 53 * (address mappings, register initial values, etc.) 54 * You should know what you are doing if you make changes here. 55 */ 56 57 #define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 58 #define CFG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 59 60 /* 61 * Definitions for initial stack pointer and data area (in DPRAM) 62 */ 63 #define CFG_SYS_INIT_RAM_ADDR 0x20000000 64 #define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 65 66 /* 67 * Start addresses for the final memory configuration 68 * (Set up by the startup code) 69 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 70 */ 71 #define CFG_SYS_SDRAM_BASE 0x00000000 72 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 73 74 /* 75 * For booting Linux, the board info and command line data 76 * have to be in the first 8 MB of memory, since this is 77 * the maximum mapped by the Linux kernel during initialization ?? 78 */ 79 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) 80 81 /* FLASH organization */ 82 #define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) 83 84 #define FLASH_SST6401B 0x200 85 #define SST_ID_xF6401B 0x236D236D 86 87 #ifdef CONFIG_SYS_FLASH_CFI 88 /* 89 * Unable to use CFI driver, due to incompatible sector erase command by SST. 90 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 91 * 0x30 is block erase in SST 92 */ 93 # define CFG_SYS_FLASH_SIZE 0x800000 94 #else 95 # define CFG_SYS_SST_SECT 2048 96 # define CFG_SYS_SST_SECTSZ 0x1000 97 #endif 98 99 /* Cache Configuration */ 100 101 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ 102 CFG_SYS_INIT_RAM_SIZE - 8) 103 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ 104 CFG_SYS_INIT_RAM_SIZE - 4) 105 #define CFG_SYS_ICACHE_INV (CF_CACR_DCM) 106 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \ 107 CF_ADDRMASK(8) | \ 108 CF_ACR_EN | CF_ACR_SM_ALL) 109 #define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ 110 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ 111 CF_ACR_EN | CF_ACR_SM_ALL) 112 #define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 113 CF_CACR_DBWE) 114 115 #define CFG_SYS_CS0_BASE 0xFF800000 116 #define CFG_SYS_CS0_MASK 0x007F0021 117 #define CFG_SYS_CS0_CTRL 0x00001D80 118 119 #define CFG_SYS_CS1_BASE 0xE0000000 120 #define CFG_SYS_CS1_MASK 0x00000001 121 #define CFG_SYS_CS1_CTRL 0x00003DD8 122 123 /*----------------------------------------------------------------------- 124 * Port configuration 125 */ 126 #define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 127 #define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 128 #define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 129 #define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 130 #define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 131 #define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 132 #define CFG_SYS_GPIO1_LED 0x00400000 /* user led */ 133 134 #endif /* _M5253DEMO_H */ 135