1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Motorola MC5282EVB board. 4 * 5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 6 */ 7 8 /* 9 * board/config.h - configuration options, board specific 10 */ 11 12 #ifndef _CONFIG_M5282EVB_H 13 #define _CONFIG_M5282EVB_H 14 15 /* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20 #define CFG_SYS_UART_PORT (0) 21 22 /* Configuration for environment 23 * Environment is embedded in u-boot in the second sector of the flash 24 */ 25 26 #define LDS_BOARD_TEXT \ 27 . = DEFINED(env_offset) ? env_offset : .; \ 28 env/embedded.o(.text*); 29 30 #define CFG_EXTRA_ENV_SETTINGS \ 31 "netdev=eth0\0" \ 32 "loadaddr=10000\0" \ 33 "u-boot=u-boot.bin\0" \ 34 "load=tftp ${loadaddr) ${u-boot}\0" \ 35 "upd=run load; run prog\0" \ 36 "prog=prot off ffe00000 ffe3ffff;" \ 37 "era ffe00000 ffe3ffff;" \ 38 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 39 "save\0" \ 40 "" 41 42 #define CFG_SYS_CLK 64000000 43 44 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ 45 46 #define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 47 #define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 48 49 /* 50 * Low Level Configuration Settings 51 * (address mappings, register initial values, etc.) 52 * You should know what you are doing if you make changes here. 53 */ 54 #define CFG_SYS_MBAR 0x40000000 55 56 /*----------------------------------------------------------------------- 57 * Definitions for initial stack pointer and data area (in DPRAM) 58 */ 59 #define CFG_SYS_INIT_RAM_ADDR 0x20000000 60 #define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 61 62 /*----------------------------------------------------------------------- 63 * Start addresses for the final memory configuration 64 * (Set up by the startup code) 65 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 66 */ 67 #define CFG_SYS_SDRAM_BASE 0x00000000 68 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 69 #define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE 70 #define CFG_SYS_INT_FLASH_BASE 0xf0000000 71 #define CFG_SYS_INT_FLASH_ENABLE 0x21 72 73 /* 74 * For booting Linux, the board info and command line data 75 * have to be in the first 8 MB of memory, since this is 76 * the maximum mapped by the Linux kernel during initialization ?? 77 */ 78 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) 79 80 /*----------------------------------------------------------------------- 81 * FLASH organization 82 */ 83 #ifdef CONFIG_SYS_FLASH_CFI 84 85 # define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 86 # define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } 87 #endif 88 89 /*----------------------------------------------------------------------- 90 * Cache Configuration 91 */ 92 93 #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ 94 CFG_SYS_INIT_RAM_SIZE - 8) 95 #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ 96 CFG_SYS_INIT_RAM_SIZE - 4) 97 #define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 98 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ 99 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ 100 CF_ACR_EN | CF_ACR_SM_ALL) 101 #define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 102 CF_CACR_CEIB | CF_CACR_DBWE | \ 103 CF_CACR_EUSP) 104 105 /*----------------------------------------------------------------------- 106 * Memory bank definitions 107 */ 108 #define CFG_SYS_CS0_BASE 0xFFE00000 109 #define CFG_SYS_CS0_CTRL 0x00001980 110 #define CFG_SYS_CS0_MASK 0x001F0001 111 112 /*----------------------------------------------------------------------- 113 * Port configuration 114 */ 115 #define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 116 #define CFG_SYS_PADDR 0x0000000 117 #define CFG_SYS_PADAT 0x0000000 118 119 #define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 120 #define CFG_SYS_PBDDR 0x0000000 121 #define CFG_SYS_PBDAT 0x0000000 122 123 #define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 124 125 #define CFG_SYS_PEHLPAR 0xC0 126 #define CFG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ 127 #define CFG_SYS_DDRUA 0x05 128 #define CFG_SYS_PJPAR 0xFF 129 130 #endif /* _CONFIG_M5282EVB_H */ 131