1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 * Copyright 2020-2021 NXP 5 */ 6 7 /* 8 * P2041 RDB board configuration file 9 * Also supports P2040 RDB 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #define CFG_RESET_VECTOR_ADDRESS 0xfffffffc 16 #endif 17 18 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 19 /* Set 1M boot space */ 20 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) 21 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 22 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 23 #define CFG_RESET_VECTOR_ADDRESS 0xfffffffc 24 #endif 25 26 /* High Level Configuration Options */ 27 28 #ifndef CFG_RESET_VECTOR_ADDRESS 29 #define CFG_RESET_VECTOR_ADDRESS 0xeffffffc 30 #endif 31 32 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 33 34 #ifndef __ASSEMBLY__ 35 #include <linux/stringify.h> 36 #endif 37 38 /* 39 * These can be toggled for performance analysis, otherwise use default. 40 */ 41 #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E 42 43 #define CFG_POST CFG_SYS_POST_MEMORY /* test POST memory test */ 44 45 /* 46 * Config the L3 Cache as L3 SRAM 47 */ 48 #define CFG_SYS_INIT_L3_ADDR CONFIG_TEXT_BASE 49 #ifdef CONFIG_PHYS_64BIT 50 #define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_TEXT_BASE) 51 #else 52 #define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR 53 #endif 54 55 #ifdef CONFIG_PHYS_64BIT 56 #define CFG_SYS_DCSRBAR 0xf0000000 57 #define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull 58 #endif 59 60 /* 61 * DDR Setup 62 */ 63 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 64 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 65 66 #define SPD_EEPROM_ADDRESS 0x52 67 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 68 69 /* 70 * Local Bus Definitions 71 */ 72 73 /* Set the local bus clock 1/8 of platform clock */ 74 #define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8 75 76 /* 77 * This board doesn't have a promjet connector. 78 * However, it uses commone corenet board LAW and TLB. 79 * It is necessary to use the same start address with proper offset. 80 */ 81 #define CFG_SYS_FLASH_BASE 0xe0000000 82 #ifdef CONFIG_PHYS_64BIT 83 #define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 84 #else 85 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE 86 #endif 87 88 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 89 #ifdef CONFIG_PHYS_64BIT 90 #define CPLD_BASE_PHYS 0xfffdf0000ull 91 #else 92 #define CPLD_BASE_PHYS CPLD_BASE 93 #endif 94 95 #define PIXIS_LBMAP_SWITCH 7 96 #define PIXIS_LBMAP_MASK 0xf0 97 #define PIXIS_LBMAP_SHIFT 4 98 #define PIXIS_LBMAP_ALTBANK 0x40 99 100 /* Nand Flash */ 101 #ifdef CONFIG_NAND_FSL_ELBC 102 #define CFG_SYS_NAND_BASE 0xffa00000 103 #ifdef CONFIG_PHYS_64BIT 104 #define CFG_SYS_NAND_BASE_PHYS 0xfffa00000ull 105 #else 106 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE 107 #endif 108 109 #define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE} 110 111 /* NAND flash config */ 112 #define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ 113 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 114 | BR_PS_8 /* Port Size = 8 bit */ \ 115 | BR_MS_FCM /* MSEL = FCM */ \ 116 | BR_V) /* valid */ 117 #define CFG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 118 | OR_FCM_PGS /* Large Page*/ \ 119 | OR_FCM_CSCT \ 120 | OR_FCM_CST \ 121 | OR_FCM_CHT \ 122 | OR_FCM_SCY_1 \ 123 | OR_FCM_TRLX \ 124 | OR_FCM_EHTR) 125 #endif /* CONFIG_NAND_FSL_ELBC */ 126 127 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000} 128 129 /* define to use L1 as initial stack */ 130 #define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 131 #ifdef CONFIG_PHYS_64BIT 132 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 133 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR 134 /* The assembler doesn't like typecast */ 135 #define CFG_SYS_INIT_RAM_ADDR_PHYS \ 136 ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 137 CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) 138 #else 139 #define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR 140 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 141 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS 142 #endif 143 #define CFG_SYS_INIT_RAM_SIZE 0x00004000 144 145 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 146 147 /* Serial Port - controlled on board with jumper J8 148 * open - index 2 149 * shorted - index 1 150 */ 151 152 #define CFG_SYS_BAUDRATE_TABLE \ 153 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 154 155 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) 156 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) 157 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) 158 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) 159 160 /* I2C */ 161 162 /* 163 * RapidIO 164 */ 165 #define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 166 #ifdef CONFIG_PHYS_64BIT 167 #define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 168 #else 169 #define CFG_SYS_SRIO1_MEM_PHYS 0xa0000000 170 #endif 171 #define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 172 173 #define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 174 #ifdef CONFIG_PHYS_64BIT 175 #define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 176 #else 177 #define CFG_SYS_SRIO2_MEM_PHYS 0xb0000000 178 #endif 179 #define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 180 181 /* 182 * for slave u-boot IMAGE instored in master memory space, 183 * PHYS must be aligned based on the SIZE 184 */ 185 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 186 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 187 #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 188 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 189 /* 190 * for slave UCODE and ENV instored in master memory space, 191 * PHYS must be aligned based on the SIZE 192 */ 193 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 194 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 195 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 196 197 /* slave core release by master*/ 198 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 199 #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 200 201 /* 202 * SRIO_PCIE_BOOT - SLAVE 203 */ 204 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 205 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 206 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 207 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 208 #endif 209 210 /* 211 * eSPI - Enhanced SPI 212 */ 213 214 /* 215 * General PCI 216 * Memory space is mapped 1-1, but I/O space must start from 0. 217 */ 218 219 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 220 #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 221 #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 222 #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 223 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull 224 225 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 226 #define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 227 #define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 228 #define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 229 #define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull 230 231 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 232 #define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000 233 #define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 234 235 /* Qman/Bman */ 236 #define CFG_SYS_BMAN_NUM_PORTALS 10 237 #define CFG_SYS_BMAN_MEM_BASE 0xf4000000 238 #ifdef CONFIG_PHYS_64BIT 239 #define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull 240 #else 241 #define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE 242 #endif 243 #define CFG_SYS_BMAN_MEM_SIZE 0x00200000 244 #define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 245 #define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 246 #define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE 247 #define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) 248 #define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ 249 CFG_SYS_BMAN_CENA_SIZE) 250 #define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) 251 #define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 252 #define CFG_SYS_QMAN_NUM_PORTALS 10 253 #define CFG_SYS_QMAN_MEM_BASE 0xf4200000 254 #ifdef CONFIG_PHYS_64BIT 255 #define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull 256 #else 257 #define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE 258 #endif 259 #define CFG_SYS_QMAN_MEM_SIZE 0x00200000 260 #define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 261 #define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) 262 #define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ 263 CFG_SYS_QMAN_CENA_SIZE) 264 #define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) 265 #define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 266 267 #ifdef CONFIG_FMAN_ENET 268 #define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 269 #define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 270 #define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 271 #define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 272 #define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 273 274 #define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 275 #define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 276 #define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 277 #define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 278 279 #define CFG_SYS_FM1_10GEC1_PHY_ADDR 0 280 281 #define CFG_SYS_TBIPA_VALUE 8 282 #endif 283 284 #ifdef CONFIG_MMC 285 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR 286 #endif 287 288 /* 289 * Miscellaneous configurable options 290 */ 291 292 /* 293 * For booting Linux, the board info and command line data 294 * have to be in the first 64 MB of memory, since this is 295 * the maximum mapped by the Linux kernel during initialization. 296 */ 297 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 298 299 /* 300 * Environment Configuration 301 */ 302 303 #define __USB_PHY_TYPE utmi 304 305 #define CFG_EXTRA_ENV_SETTINGS \ 306 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 307 "bank_intlv=cs0_cs1\0" \ 308 "netdev=eth0\0" \ 309 "uboot=" CONFIG_UBOOTPATH "\0" \ 310 "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ 311 "tftpflash=tftpboot $loadaddr $uboot && " \ 312 "protect off $ubootaddr +$filesize && " \ 313 "erase $ubootaddr +$filesize && " \ 314 "cp.b $loadaddr $ubootaddr $filesize && " \ 315 "protect on $ubootaddr +$filesize && " \ 316 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 317 "consoledev=ttyS0\0" \ 318 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 319 "usb_dr_mode=host\0" \ 320 "ramdiskaddr=2000000\0" \ 321 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 322 "fdtaddr=1e00000\0" \ 323 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 324 "bdev=sda3\0" 325 326 #include <asm/fsl_secure_boot.h> 327 328 #endif /* __CONFIG_H */ 329