1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * Copyright 2020-2023 NXP 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 #include <linux/stringify.h> 15 16 /* High Level Configuration Options */ 17 18 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 19 20 #ifdef CONFIG_RAMBOOT_PBL 21 #define RESET_VECTOR_OFFSET 0x27FFC 22 #define BOOT_PAGE_OFFSET 0x27000 23 24 #ifdef CONFIG_MTD_RAW_NAND 25 #define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) 26 #define CFG_SYS_NAND_U_BOOT_DST 0x30000000 27 #define CFG_SYS_NAND_U_BOOT_START 0x30000000 28 #endif 29 30 #ifdef CONFIG_SPIFLASH 31 #define CFG_RESET_VECTOR_ADDRESS 0x30000FFC 32 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 33 #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 34 #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 35 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 36 #endif 37 38 #ifdef CONFIG_SDCARD 39 #define CFG_RESET_VECTOR_ADDRESS 0x30000FFC 40 #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) 41 #define CFG_SYS_MMC_U_BOOT_DST (0x30000000) 42 #define CFG_SYS_MMC_U_BOOT_START (0x30000000) 43 #define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) 44 #endif 45 46 #endif /* CONFIG_RAMBOOT_PBL */ 47 48 #ifndef CFG_RESET_VECTOR_ADDRESS 49 #define CFG_RESET_VECTOR_ADDRESS 0xeffffffc 50 #endif 51 52 /* 53 * for slave u-boot IMAGE instored in master memory space, 54 * PHYS must be aligned based on the SIZE 55 */ 56 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 57 #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 58 #ifdef CONFIG_PHYS_64BIT 59 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 60 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 61 #else 62 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 63 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 64 #endif 65 /* 66 * for slave UCODE and ENV instored in master memory space, 67 * PHYS must be aligned based on the SIZE 68 */ 69 #ifdef CONFIG_PHYS_64BIT 70 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 71 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 72 #else 73 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 74 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 75 #endif 76 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 77 /* slave core release by master*/ 78 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 79 #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 80 81 /* PCIe Boot - Slave */ 82 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 83 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 84 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 85 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 86 /* Set 1M boot space for PCIe boot */ 87 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) 88 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 89 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 90 #define CFG_RESET_VECTOR_ADDRESS 0xfffffffc 91 #endif 92 93 /* 94 * These can be toggled for performance analysis, otherwise use default. 95 */ 96 #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E 97 98 /* 99 * Config the L3 Cache as L3 SRAM 100 */ 101 #define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 102 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 103 104 #ifdef CONFIG_PHYS_64BIT 105 #define CFG_SYS_DCSRBAR 0xf0000000 106 #define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull 107 #endif 108 109 /* 110 * DDR Setup 111 */ 112 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 113 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 114 #if defined(CONFIG_TARGET_T1024RDB) 115 #define SPD_EEPROM_ADDRESS 0x51 116 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 117 #elif defined(CONFIG_TARGET_T1023RDB) 118 #define CFG_SYS_SDRAM_SIZE 2048 119 #endif 120 121 /* 122 * IFC Definitions 123 */ 124 #define CFG_SYS_FLASH_BASE 0xe8000000 125 #ifdef CONFIG_PHYS_64BIT 126 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) 127 #else 128 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE 129 #endif 130 131 #define CFG_SYS_NOR0_CSPR_EXT (0xf) 132 #define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ 133 CSPR_PORT_SIZE_16 | \ 134 CSPR_MSEL_NOR | \ 135 CSPR_V) 136 #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 137 138 /* NOR Flash Timing Params */ 139 #if defined(CONFIG_TARGET_T1024RDB) 140 #define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 141 #elif defined(CONFIG_TARGET_T1023RDB) 142 #define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 143 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 144 #endif 145 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 146 FTIM0_NOR_TEADC(0x5) | \ 147 FTIM0_NOR_TEAHC(0x5)) 148 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 149 FTIM1_NOR_TRAD_NOR(0x1A) |\ 150 FTIM1_NOR_TSEQRAD_NOR(0x13)) 151 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 152 FTIM2_NOR_TCH(0x4) | \ 153 FTIM2_NOR_TWPH(0x0E) | \ 154 FTIM2_NOR_TWP(0x1c)) 155 #define CFG_SYS_NOR_FTIM3 0x0 156 157 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} 158 159 #ifdef CONFIG_TARGET_T1024RDB 160 /* CPLD on IFC */ 161 #define CFG_SYS_CPLD_BASE 0xffdf0000 162 #define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) 163 #define CFG_SYS_CSPR2_EXT (0xf) 164 #define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \ 165 | CSPR_PORT_SIZE_8 \ 166 | CSPR_MSEL_GPCM \ 167 | CSPR_V) 168 #define CFG_SYS_AMASK2 IFC_AMASK(64*1024) 169 #define CFG_SYS_CSOR2 0x0 170 171 /* CPLD Timing parameters for IFC CS2 */ 172 #define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 173 FTIM0_GPCM_TEADC(0x0e) | \ 174 FTIM0_GPCM_TEAHC(0x0e)) 175 #define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 176 FTIM1_GPCM_TRAD(0x1f)) 177 #define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 178 FTIM2_GPCM_TCH(0x8) | \ 179 FTIM2_GPCM_TWP(0x1f)) 180 #define CFG_SYS_CS2_FTIM3 0x0 181 #endif 182 183 /* NAND Flash on IFC */ 184 #define CFG_SYS_NAND_BASE 0xff800000 185 #ifdef CONFIG_PHYS_64BIT 186 #define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) 187 #else 188 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE 189 #endif 190 #define CFG_SYS_NAND_CSPR_EXT (0xf) 191 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ 192 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 193 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 194 | CSPR_V) 195 #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) 196 197 #if defined(CONFIG_TARGET_T1024RDB) 198 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 199 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 200 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 201 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 202 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 203 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 204 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 205 #elif defined(CONFIG_TARGET_T1023RDB) 206 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 207 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 208 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 209 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 210 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 211 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 212 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 213 #endif 214 215 /* ONFI NAND Flash mode0 Timing Params */ 216 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 217 FTIM0_NAND_TWP(0x18) | \ 218 FTIM0_NAND_TWCHT(0x07) | \ 219 FTIM0_NAND_TWH(0x0a)) 220 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 221 FTIM1_NAND_TWBE(0x39) | \ 222 FTIM1_NAND_TRR(0x0e) | \ 223 FTIM1_NAND_TRP(0x18)) 224 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 225 FTIM2_NAND_TREH(0x0a) | \ 226 FTIM2_NAND_TWHRE(0x1e)) 227 #define CFG_SYS_NAND_FTIM3 0x0 228 229 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 230 231 #if defined(CONFIG_MTD_RAW_NAND) 232 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT 233 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR 234 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK 235 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR 236 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 237 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 238 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 239 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 240 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT 241 #define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR 242 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK 243 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR 244 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 245 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 246 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 247 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 248 #else 249 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT 250 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR 251 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK 252 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR 253 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 254 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 255 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 256 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 257 #define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT 258 #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR 259 #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK 260 #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR 261 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 262 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 263 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 264 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 265 #endif 266 267 /* define to use L1 as initial stack */ 268 #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 269 #ifdef CONFIG_PHYS_64BIT 270 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 271 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 272 /* The assembler doesn't like typecast */ 273 #define CFG_SYS_INIT_RAM_ADDR_PHYS \ 274 ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 275 CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) 276 #else 277 #define CFG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 278 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 279 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS 280 #endif 281 #define CFG_SYS_INIT_RAM_SIZE 0x00004000 282 283 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 284 285 /* Serial Port */ 286 #if !CONFIG_IS_ENABLED(DM_SERIAL) 287 #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) 288 #endif 289 290 #define CFG_SYS_BAUDRATE_TABLE \ 291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 292 293 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) 294 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) 295 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) 296 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) 297 298 /* I2C */ 299 300 #define I2C_PCA6408_BUS_NUM 1 301 #define I2C_PCA6408_ADDR 0x20 302 303 /* I2C bus multiplexer */ 304 #define I2C_MUX_CH_DEFAULT 0x8 305 306 /* 307 * RTC configuration 308 */ 309 #define CFG_SYS_I2C_RTC_ADDR 0x68 310 311 /* 312 * eSPI - Enhanced SPI 313 */ 314 315 /* 316 * General PCIe 317 * Memory space is mapped 1-1, but I/O space must start from 0. 318 */ 319 320 #ifdef CONFIG_PCI 321 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 322 #ifdef CONFIG_PCIE1 323 #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 324 #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 325 #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 326 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull 327 #endif 328 329 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 330 #ifdef CONFIG_PCIE2 331 #define CFG_SYS_PCIE2_MEM_VIRT 0x90000000 332 #define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 333 #define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 334 #define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull 335 #endif 336 337 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 338 #ifdef CONFIG_PCIE3 339 #define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000 340 #define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 341 #endif 342 #endif /* CONFIG_PCI */ 343 344 /* 345 * USB 346 */ 347 348 /* 349 * SDHC 350 */ 351 #ifdef CONFIG_MMC 352 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR 353 #endif 354 355 /* Qman/Bman */ 356 #ifndef CONFIG_NOBQFMAN 357 #define CFG_SYS_BMAN_NUM_PORTALS 10 358 #define CFG_SYS_BMAN_MEM_BASE 0xf4000000 359 #ifdef CONFIG_PHYS_64BIT 360 #define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull 361 #else 362 #define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE 363 #endif 364 #define CFG_SYS_BMAN_MEM_SIZE 0x02000000 365 #define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 366 #define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 367 #define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE 368 #define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) 369 #define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ 370 CFG_SYS_BMAN_CENA_SIZE) 371 #define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) 372 #define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 373 #define CFG_SYS_QMAN_NUM_PORTALS 10 374 #define CFG_SYS_QMAN_MEM_BASE 0xf6000000 375 #ifdef CONFIG_PHYS_64BIT 376 #define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull 377 #else 378 #define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE 379 #endif 380 #define CFG_SYS_QMAN_MEM_SIZE 0x02000000 381 #define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 382 #define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) 383 #define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ 384 CFG_SYS_QMAN_CENA_SIZE) 385 #define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) 386 #define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 387 388 #endif /* CONFIG_NOBQFMAN */ 389 390 #ifdef CONFIG_SYS_DPAA_FMAN 391 #if defined(CONFIG_TARGET_T1024RDB) 392 #define RGMII_PHY1_ADDR 0x2 393 #define RGMII_PHY2_ADDR 0x6 394 #define SGMII_AQR_PHY_ADDR 0x2 395 #define FM1_10GEC1_PHY_ADDR 0x1 396 #elif defined(CONFIG_TARGET_T1023RDB) 397 #define RGMII_PHY1_ADDR 0x1 398 #define SGMII_RTK_PHY_ADDR 0x3 399 #define SGMII_AQR_PHY_ADDR 0x2 400 #endif 401 #endif 402 403 /* 404 * Dynamic MTD Partition support with mtdparts 405 */ 406 407 /* 408 * Miscellaneous configurable options 409 */ 410 411 /* 412 * For booting Linux, the board info and command line data 413 * have to be in the first 64 MB of memory, since this is 414 * the maximum mapped by the Linux kernel during initialization. 415 */ 416 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 417 418 /* 419 * Environment Configuration 420 */ 421 #define __USB_PHY_TYPE utmi 422 423 #ifdef CONFIG_ARCH_T1024 424 #define ARCH_EXTRA_ENV_SETTINGS \ 425 "bank_intlv=cs0_cs1\0" \ 426 "ramdiskfile=t1024rdb/ramdisk.uboot\0" \ 427 "fdtfile=t1024rdb/t1024rdb.dtb\0" 428 #else 429 #define ARCH_EXTRA_ENV_SETTINGS \ 430 "bank_intlv=null\0" \ 431 "ramdiskfile=t1023rdb/ramdisk.uboot\0" \ 432 "fdtfile=t1023rdb/t1023rdb.dtb\0" 433 #endif 434 435 #define CFG_EXTRA_ENV_SETTINGS \ 436 ARCH_EXTRA_ENV_SETTINGS \ 437 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 438 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 439 "uboot=" CONFIG_UBOOTPATH "\0" \ 440 "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ 441 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 442 "netdev=eth0\0" \ 443 "tftpflash=tftpboot $loadaddr $uboot && " \ 444 "protect off $ubootaddr +$filesize && " \ 445 "erase $ubootaddr +$filesize && " \ 446 "cp.b $loadaddr $ubootaddr $filesize && " \ 447 "protect on $ubootaddr +$filesize && " \ 448 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 449 "consoledev=ttyS0\0" \ 450 "ramdiskaddr=2000000\0" \ 451 "fdtaddr=1e00000\0" \ 452 "bdev=sda3\0" 453 454 #include <asm/fsl_secure_boot.h> 455 456 #endif /* __T1024RDB_H */ 457