1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2013 Freescale Semiconductor, Inc. 4 * Copyright 2020-2021 NXP 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #include <linux/stringify.h> 15 16 #define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 /* High Level Configuration Options */ 19 20 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 21 22 #ifdef CONFIG_RAMBOOT_PBL 23 #define RESET_VECTOR_OFFSET 0x27FFC 24 #define BOOT_PAGE_OFFSET 0x27000 25 26 #ifdef CONFIG_MTD_RAW_NAND 27 #define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) 28 #define CFG_SYS_NAND_U_BOOT_DST 0x00200000 29 #define CFG_SYS_NAND_U_BOOT_START 0x00200000 30 #endif 31 32 #ifdef CONFIG_SPIFLASH 33 #define CFG_RESET_VECTOR_ADDRESS 0x200FFC 34 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 35 #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 36 #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 37 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 38 #endif 39 40 #ifdef CONFIG_SDCARD 41 #define CFG_RESET_VECTOR_ADDRESS 0x200FFC 42 #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) 43 #define CFG_SYS_MMC_U_BOOT_DST (0x00200000) 44 #define CFG_SYS_MMC_U_BOOT_START (0x00200000) 45 #define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) 46 #endif 47 48 #endif /* CONFIG_RAMBOOT_PBL */ 49 50 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 51 /* Set 1M boot space */ 52 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) 53 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 54 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 55 #define CFG_RESET_VECTOR_ADDRESS 0xfffffffc 56 #endif 57 58 #ifndef CFG_RESET_VECTOR_ADDRESS 59 #define CFG_RESET_VECTOR_ADDRESS 0xeffffffc 60 #endif 61 62 /* 63 * Config the L3 Cache as L3 SRAM 64 */ 65 #define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 66 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 67 68 #define CFG_SYS_DCSRBAR 0xf0000000 69 #define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull 70 71 /* 72 * DDR Setup 73 */ 74 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 75 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 76 #define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 77 #define SPD_EEPROM_ADDRESS1 0x51 78 #define SPD_EEPROM_ADDRESS2 0x52 79 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 80 #define CTRL_INTLV_PREFERED cacheline 81 82 /* 83 * IFC Definitions 84 */ 85 #define CFG_SYS_FLASH_BASE 0xe0000000 86 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) 87 #define CFG_SYS_NOR0_CSPR_EXT (0xf) 88 #define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ 89 + 0x8000000) | \ 90 CSPR_PORT_SIZE_16 | \ 91 CSPR_MSEL_NOR | \ 92 CSPR_V) 93 #define CFG_SYS_NOR1_CSPR_EXT (0xf) 94 #define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ 95 CSPR_PORT_SIZE_16 | \ 96 CSPR_MSEL_NOR | \ 97 CSPR_V) 98 #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 99 /* NOR Flash Timing Params */ 100 #define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 101 102 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 103 FTIM0_NOR_TEADC(0x5) | \ 104 FTIM0_NOR_TEAHC(0x5)) 105 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 106 FTIM1_NOR_TRAD_NOR(0x1A) |\ 107 FTIM1_NOR_TSEQRAD_NOR(0x13)) 108 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 109 FTIM2_NOR_TCH(0x4) | \ 110 FTIM2_NOR_TWPH(0x0E) | \ 111 FTIM2_NOR_TWP(0x1c)) 112 #define CFG_SYS_NOR_FTIM3 0x0 113 114 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ 115 + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} 116 117 #define QIXIS_BASE 0xffdf0000 118 #define QIXIS_LBMAP_SWITCH 6 119 #define QIXIS_LBMAP_MASK 0x0f 120 #define QIXIS_LBMAP_SHIFT 0 121 #define QIXIS_LBMAP_DFLTBANK 0x00 122 #define QIXIS_LBMAP_ALTBANK 0x04 123 #define QIXIS_LBMAP_NAND 0x09 124 #define QIXIS_LBMAP_SD 0x00 125 #define QIXIS_RCW_SRC_NAND 0x104 126 #define QIXIS_RCW_SRC_SD 0x040 127 #define QIXIS_RST_CTL_RESET 0x83 128 #define QIXIS_RST_FORCE_MEM 0x1 129 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 130 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 131 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 132 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 133 134 #define CFG_SYS_CSPR3_EXT (0xf) 135 #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 136 | CSPR_PORT_SIZE_8 \ 137 | CSPR_MSEL_GPCM \ 138 | CSPR_V) 139 #define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) 140 #define CFG_SYS_CSOR3 0x0 141 /* QIXIS Timing parameters for IFC CS3 */ 142 #define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 143 FTIM0_GPCM_TEADC(0x0e) | \ 144 FTIM0_GPCM_TEAHC(0x0e)) 145 #define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 146 FTIM1_GPCM_TRAD(0x3f)) 147 #define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 148 FTIM2_GPCM_TCH(0x8) | \ 149 FTIM2_GPCM_TWP(0x1f)) 150 #define CFG_SYS_CS3_FTIM3 0x0 151 152 /* NAND Flash on IFC */ 153 #define CFG_SYS_NAND_BASE 0xff800000 154 #define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) 155 156 #define CFG_SYS_NAND_CSPR_EXT (0xf) 157 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ 158 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 159 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 160 | CSPR_V) 161 #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) 162 163 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 164 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 165 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 166 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 167 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 168 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 169 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 170 171 /* ONFI NAND Flash mode0 Timing Params */ 172 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 173 FTIM0_NAND_TWP(0x18) | \ 174 FTIM0_NAND_TWCHT(0x07) | \ 175 FTIM0_NAND_TWH(0x0a)) 176 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 177 FTIM1_NAND_TWBE(0x39) | \ 178 FTIM1_NAND_TRR(0x0e) | \ 179 FTIM1_NAND_TRP(0x18)) 180 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 181 FTIM2_NAND_TREH(0x0a) | \ 182 FTIM2_NAND_TWHRE(0x1e)) 183 #define CFG_SYS_NAND_FTIM3 0x0 184 185 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 186 187 #if defined(CONFIG_MTD_RAW_NAND) 188 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT 189 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR 190 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK 191 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR 192 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 193 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 194 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 195 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 196 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT 197 #define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR 198 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK 199 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR 200 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 201 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 202 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 203 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 204 #define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT 205 #define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR 206 #define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK 207 #define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR 208 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 209 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 210 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 211 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 212 #else 213 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT 214 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR 215 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK 216 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR 217 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 218 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 219 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 220 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 221 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT 222 #define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR 223 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK 224 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR 225 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 226 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 227 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 228 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 229 #define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT 230 #define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR 231 #define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK 232 #define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR 233 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 234 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 235 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 236 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 237 #endif 238 239 /* define to use L1 as initial stack */ 240 #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 241 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 242 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 243 /* The assembler doesn't like typecast */ 244 #define CFG_SYS_INIT_RAM_ADDR_PHYS \ 245 ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 246 CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) 247 #define CFG_SYS_INIT_RAM_SIZE 0x00004000 248 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 249 250 /* 251 * Serial Port 252 */ 253 #define CFG_SYS_BAUDRATE_TABLE \ 254 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 255 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) 256 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) 257 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) 258 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) 259 260 /* 261 * I2C 262 */ 263 264 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 265 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 266 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 267 #define I2C_MUX_CH_DEFAULT 0x8 268 269 #define I2C_MUX_CH_VOL_MONITOR 0xa 270 271 /* Voltage monitor on channel 2*/ 272 #define I2C_VOL_MONITOR_ADDR 0x40 273 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 274 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 275 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 276 277 /* The lowest and highest voltage allowed for T208xQDS */ 278 #define VDD_MV_MIN 819 279 #define VDD_MV_MAX 1212 280 281 /* 282 * RapidIO 283 */ 284 #define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 285 #define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 286 #define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 287 #define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 288 #define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 289 #define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 290 /* 291 * for slave u-boot IMAGE instored in master memory space, 292 * PHYS must be aligned based on the SIZE 293 */ 294 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 295 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 296 #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 297 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 298 /* 299 * for slave UCODE and ENV instored in master memory space, 300 * PHYS must be aligned based on the SIZE 301 */ 302 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 303 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 304 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 305 306 /* slave core release by master*/ 307 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 308 #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 309 310 /* 311 * SRIO_PCIE_BOOT - SLAVE 312 */ 313 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 314 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 315 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 316 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 317 #endif 318 319 /* 320 * eSPI - Enhanced SPI 321 */ 322 323 /* 324 * General PCI 325 * Memory space is mapped 1-1, but I/O space must start from 0. 326 */ 327 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 328 #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 329 #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 330 #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 331 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull 332 333 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 334 #define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 335 #define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 336 #define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 337 #define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull 338 339 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 340 #define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000 341 #define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 342 343 /* controller 4, Base address 203000 */ 344 #define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000 345 #define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 346 347 /* Qman/Bman */ 348 #ifndef CONFIG_NOBQFMAN 349 #define CFG_SYS_BMAN_NUM_PORTALS 18 350 #define CFG_SYS_BMAN_MEM_BASE 0xf4000000 351 #define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull 352 #define CFG_SYS_BMAN_MEM_SIZE 0x02000000 353 #define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 354 #define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 355 #define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE 356 #define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) 357 #define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ 358 CFG_SYS_BMAN_CENA_SIZE) 359 #define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) 360 #define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 361 #define CFG_SYS_QMAN_NUM_PORTALS 18 362 #define CFG_SYS_QMAN_MEM_BASE 0xf6000000 363 #define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull 364 #define CFG_SYS_QMAN_MEM_SIZE 0x02000000 365 #define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 366 #define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) 367 #define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ 368 CFG_SYS_QMAN_CENA_SIZE) 369 #define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) 370 #define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 371 #endif /* CONFIG_NOBQFMAN */ 372 373 #ifdef CONFIG_SYS_DPAA_FMAN 374 #define RGMII_PHY1_ADDR 0x1 375 #define RGMII_PHY2_ADDR 0x2 376 #define FM1_10GEC1_PHY_ADDR 0x3 377 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 378 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 379 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 380 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 381 #endif 382 383 /* 384 * USB 385 */ 386 387 /* 388 * SDHC 389 */ 390 #ifdef CONFIG_MMC 391 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR 392 #endif 393 394 /* 395 * Dynamic MTD Partition support with mtdparts 396 */ 397 398 /* 399 * Miscellaneous configurable options 400 */ 401 402 /* 403 * For booting Linux, the board info and command line data 404 * have to be in the first 64 MB of memory, since this is 405 * the maximum mapped by the Linux kernel during initialization. 406 */ 407 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 408 409 /* 410 * Environment Configuration 411 */ 412 413 #define __USB_PHY_TYPE utmi 414 415 #define CFG_EXTRA_ENV_SETTINGS \ 416 "hwconfig=fsl_ddr:" \ 417 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 418 "bank_intlv=auto;" \ 419 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 420 "netdev=eth0\0" \ 421 "uboot=" CONFIG_UBOOTPATH "\0" \ 422 "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ 423 "tftpflash=tftpboot $loadaddr $uboot && " \ 424 "protect off $ubootaddr +$filesize && " \ 425 "erase $ubootaddr +$filesize && " \ 426 "cp.b $loadaddr $ubootaddr $filesize && " \ 427 "protect on $ubootaddr +$filesize && " \ 428 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 429 "consoledev=ttyS0\0" \ 430 "ramdiskaddr=2000000\0" \ 431 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 432 "fdtaddr=1e00000\0" \ 433 "fdtfile=t2080qds/t2080qds.dtb\0" \ 434 "bdev=sda3\0" 435 436 /* 437 * For emulation this causes u-boot to jump to the start of the 438 * proof point app code automatically 439 */ 440 #define PROOF_POINTS \ 441 "setenv bootargs root=/dev/$bdev rw " \ 442 "console=$consoledev,$baudrate $othbootargs;" \ 443 "cpu 1 release 0x29000000 - - -;" \ 444 "cpu 2 release 0x29000000 - - -;" \ 445 "cpu 3 release 0x29000000 - - -;" \ 446 "cpu 4 release 0x29000000 - - -;" \ 447 "cpu 5 release 0x29000000 - - -;" \ 448 "cpu 6 release 0x29000000 - - -;" \ 449 "cpu 7 release 0x29000000 - - -;" \ 450 "go 0x29000000" 451 452 #define HVBOOT \ 453 "setenv bootargs config-addr=0x60000000; " \ 454 "bootm 0x01000000 - 0x00f00000" 455 456 #define ALU \ 457 "setenv bootargs root=/dev/$bdev rw " \ 458 "console=$consoledev,$baudrate $othbootargs;" \ 459 "cpu 1 release 0x01000000 - - -;" \ 460 "cpu 2 release 0x01000000 - - -;" \ 461 "cpu 3 release 0x01000000 - - -;" \ 462 "cpu 4 release 0x01000000 - - -;" \ 463 "cpu 5 release 0x01000000 - - -;" \ 464 "cpu 6 release 0x01000000 - - -;" \ 465 "cpu 7 release 0x01000000 - - -;" \ 466 "go 0x01000000" 467 468 #include <asm/fsl_secure_boot.h> 469 470 #endif /* __T208xQDS_H */ 471