1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2020 Synopsys, Inc. All rights reserved. 4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 5 */ 6 7 #ifndef _CONFIG_HSDK_H_ 8 #define _CONFIG_HSDK_H_ 9 10 #include <linux/sizes.h> 11 12 /* 13 * CPU configuration 14 */ 15 #define NR_CPUS 4 16 #define ARC_PERIPHERAL_BASE 0xF0000000 17 #define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000) 18 #define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000) 19 20 /* 21 * Memory configuration 22 */ 23 24 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000 25 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 26 #define CFG_SYS_SDRAM_SIZE SZ_1G 27 28 /* 29 * UART configuration 30 */ 31 #define CFG_SYS_NS16550_CLK 33330000 32 33 /* 34 * Ethernet PHY configuration 35 */ 36 37 /* 38 * Environment settings 39 */ 40 #define CFG_EXTRA_ENV_SETTINGS \ 41 "upgrade=if mmc rescan && " \ 42 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \ 43 "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ 44 "\"Fail to upgrade.\n" \ 45 "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \ 46 "; fi\0" \ 47 "core_mask=0xF\0" \ 48 "hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \ 49 setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \ 50 setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \ 51 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \ 52 "hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \ 53 setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \ 54 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 55 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \ 56 "hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \ 57 setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \ 58 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ 59 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \ 60 "hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \ 61 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ 62 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 63 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \ 64 "hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \ 65 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ 66 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ 67 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \ 68 "hsdk_hs48x2=run hsdk_hs47dx2;\0" \ 69 "hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \ 70 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ 71 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 72 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \ 73 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \ 74 "hsdk_hs48x3=run hsdk_hs47dx3;\0" \ 75 "hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \ 76 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ 77 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 78 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \ 79 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ 80 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \ 81 "hsdk_hs48x4=run hsdk_hs47dx4;\0" \ 82 "hsdk_hs47dx4=setenv core_mask 0xF; setenv haps_apb_location 0x1; \ 83 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ 84 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 85 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \ 86 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ 87 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \ 88 setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" 89 90 /* 91 * Environment configuration 92 */ 93 94 /* Cli configuration */ 95 96 /* 97 * Callback configuration 98 */ 99 100 #endif /* _CONFIG_HSDK_H_ */ 101