1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2017 Synopsys, Inc. All rights reserved. 4 */ 5 6 #ifndef _CONFIG_HSDK_H_ 7 #define _CONFIG_HSDK_H_ 8 9 #include <linux/sizes.h> 10 11 /* 12 * CPU configuration 13 */ 14 #define NR_CPUS 4 15 #define ARC_PERIPHERAL_BASE 0xF0000000 16 #define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000) 17 #define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000) 18 19 /* 20 * Memory configuration 21 */ 22 23 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000 24 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 25 #define CFG_SYS_SDRAM_SIZE SZ_1G 26 27 /* 28 * UART configuration 29 */ 30 #define CFG_SYS_NS16550_CLK 33330000 31 32 /* 33 * Ethernet PHY configuration 34 */ 35 36 /* 37 * Environment settings 38 */ 39 #define CFG_EXTRA_ENV_SETTINGS \ 40 "upgrade=if mmc rescan && " \ 41 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \ 42 "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ 43 "\"Fail to upgrade.\n" \ 44 "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \ 45 "; fi\0" \ 46 "core_dccm_0=0x10\0" \ 47 "core_dccm_1=0x6\0" \ 48 "core_dccm_2=0x10\0" \ 49 "core_dccm_3=0x6\0" \ 50 "core_iccm_0=0x10\0" \ 51 "core_iccm_1=0x6\0" \ 52 "core_iccm_2=0x10\0" \ 53 "core_iccm_3=0x6\0" \ 54 "core_mask=0xF\0" \ 55 "dcache_ena=0x1\0" \ 56 "icache_ena=0x1\0" \ 57 "non_volatile_limit=0xE\0" \ 58 "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \ 59 setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \ 60 setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \ 61 "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \ 62 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 63 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \ 64 "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \ 65 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ 66 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \ 67 "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \ 68 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 69 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \ 70 "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \ 71 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ 72 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \ 73 "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \ 74 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 75 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \ 76 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \ 77 "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \ 78 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 79 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \ 80 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ 81 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \ 82 "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \ 83 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 84 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \ 85 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ 86 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \ 87 setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" 88 89 /* Cli configuration */ 90 91 /* 92 * Callback configuration 93 */ 94 95 #endif /* _CONFIG_HSDK_H_ */ 96