1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2022 NXP
4  */
5 
6 #ifndef __IMX93_EVK_H
7 #define __IMX93_EVK_H
8 
9 #include <asm/arch/imx-regs.h>
10 
11 #define CFG_SYS_UBOOT_BASE	\
12 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
13 
14 #ifdef CONFIG_XPL_BUILD
15 #define CFG_MALLOC_F_ADDR		0x204D0000
16 #endif
17 
18 #ifdef CONFIG_ENV_MMC_DEVICE_INDEX
19 #define IMX93_EVK_MMC_ENV_DEV CONFIG_ENV_MMC_DEVICE_INDEX
20 #else
21 #define IMX93_EVK_MMC_ENV_DEV 0
22 #endif
23 
24 /* Link Definitions */
25 
26 #define CFG_SYS_INIT_RAM_ADDR        0x80000000
27 #define CFG_SYS_INIT_RAM_SIZE        0x200000
28 
29 #define CFG_SYS_SDRAM_BASE           0x80000000
30 #define PHYS_SDRAM                      0x80000000
31 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
32 
33 /* Using ULP WDOG for reset */
34 #define WDOG_BASE_ADDR          WDG3_BASE_ADDR
35 
36 #endif
37