1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2025 NXP
4  */
5 
6 #ifndef __IMX93_FRDM_H
7 #define __IMX93_FRDM_H
8 
9 #include <asm/arch/imx-regs.h>
10 
11 #define CFG_SYS_UBOOT_BASE	\
12 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
13 
14 #ifdef CONFIG_XPL_BUILD
15 #define CFG_MALLOC_F_ADDR		0x204D0000
16 #endif
17 
18 /* Link Definitions */
19 
20 #define CFG_SYS_INIT_RAM_ADDR		0x80000000
21 #define CFG_SYS_INIT_RAM_SIZE		0x200000
22 
23 #define CFG_SYS_SDRAM_BASE		0x80000000
24 #define PHYS_SDRAM			0x80000000
25 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
26 
27 /* Using ULP WDOG for reset */
28 #define WDOG_BASE_ADDR			WDG3_BASE_ADDR
29 
30 #endif
31