1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2020 Hitachi Power Grids. All rights reserved. 4 */ 5 6 #ifndef __CONFIG_PG_WCOM_LS102XA_H 7 #define __CONFIG_PG_WCOM_LS102XA_H 8 9 #define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 10 #define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE 11 12 #define CFG_PRAM ((CONFIG_KM_PNVRAM + \ 13 CONFIG_KM_PHRAM) >> 10) 14 15 #define PHYS_SDRAM 0x80000000 16 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 17 18 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL 19 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 20 21 #define SPD_EEPROM_ADDRESS 0x54 22 23 /* POST memory regions test */ 24 #define CFG_POST (CFG_SYS_POST_MEM_REGIONS) 25 #define CFG_POST_EXTERNAL_WORD_FUNCS 26 27 /* 28 * IFC Definitions 29 */ 30 /* NOR Flash Definitions */ 31 #define CFG_SYS_FLASH_BASE 0x60000000 32 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE 33 34 #define CFG_SYS_NOR0_CSPR_EXT (0x0) 35 #define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ 36 CSPR_PORT_SIZE_16 | \ 37 CSPR_TE | \ 38 CSPR_MSEL_NOR | \ 39 CSPR_V) 40 #define CFG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) 41 42 #define CFG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \ 43 CSOR_NOR_ADM_SHIFT(0x4) | \ 44 CSOR_NOR_NOR_MODE_ASYNC_NOR | \ 45 CSOR_NOR_TRHZ_20 | \ 46 CSOR_NOR_BCTLD) 47 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 48 FTIM0_NOR_TEADC(0x7) | \ 49 FTIM0_NOR_TAVDS(0x0) | \ 50 FTIM0_NOR_TEAHC(0x1)) 51 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 52 FTIM1_NOR_TRAD_NOR(0x21) | \ 53 FTIM1_NOR_TSEQRAD_NOR(0x21)) 54 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ 55 FTIM2_NOR_TCH(0x1) | \ 56 FTIM2_NOR_TWPH(0x6) | \ 57 FTIM2_NOR_TWP(0xb)) 58 #define CFG_SYS_NOR_FTIM3 0 59 60 #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } 61 62 #define CFG_SYS_WRITE_SWAPPED_DATA 63 64 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT 65 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR 66 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK 67 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR 68 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 69 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 70 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 71 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 72 73 /* NAND Flash Definitions */ 74 #define CFG_SYS_NAND_BASE 0x68000000 75 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE 76 77 #define CFG_SYS_NAND_CSPR_EXT (0x0) 78 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \ 79 CSPR_PORT_SIZE_8 | \ 80 CSPR_TE | \ 81 CSPR_MSEL_NAND | \ 82 CSPR_V) 83 #define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 84 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \ 85 | CSOR_NAND_ECC_DEC_EN \ 86 | CSOR_NAND_ECC_MODE_4 \ 87 | CSOR_NAND_RAL_3 \ 88 | CSOR_NAND_PGS_2K \ 89 | CSOR_NAND_SPRZ_64 \ 90 | CSOR_NAND_PB(64) \ 91 | CSOR_NAND_TRHZ_40 \ 92 | CSOR_NAND_BCTLD) 93 94 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ 95 FTIM0_NAND_TWP(0x8) | \ 96 FTIM0_NAND_TWCHT(0x3) | \ 97 FTIM0_NAND_TWH(0x5)) 98 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ 99 FTIM1_NAND_TWBE(0x1e) | \ 100 FTIM1_NAND_TRR(0x6) | \ 101 FTIM1_NAND_TRP(0x8)) 102 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ 103 FTIM2_NAND_TREH(0x5) | \ 104 FTIM2_NAND_TWHRE(0x3c)) 105 #define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) 106 107 #define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT 108 #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR 109 #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK 110 #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR 111 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 112 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 113 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 114 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 115 116 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 117 118 /* QRIO FPGA Definitions */ 119 #define CFG_SYS_QRIO_BASE 0x70000000 120 #define CFG_SYS_QRIO_BASE_PHYS CFG_SYS_QRIO_BASE 121 122 #define CFG_SYS_CSPR2_EXT (0x00) 123 #define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \ 124 CSPR_PORT_SIZE_8 | \ 125 CSPR_TE | \ 126 CSPR_MSEL_GPCM | \ 127 CSPR_V) 128 #define CFG_SYS_AMASK2 IFC_AMASK(64 * 1024) 129 #define CFG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ 130 CSOR_GPCM_TRHZ_20 | \ 131 CSOR_GPCM_BCTLD) 132 #define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ 133 FTIM0_GPCM_TEADC(0x8) | \ 134 FTIM0_GPCM_TEAHC(0x2)) 135 #define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ 136 FTIM1_GPCM_TRAD(0x6)) 137 #define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ 138 FTIM2_GPCM_TCH(0x1) | \ 139 FTIM2_GPCM_TWP(0x7)) 140 #define CFG_SYS_CS2_FTIM3 0x04000000 141 142 /* 143 * Serial Port 144 */ 145 #define CFG_SYS_NS16550_CLK get_serial_clock() 146 147 #define CFG_SMP_PEN_ADDR 0x01ee0200 148 149 #define HWCONFIG_BUFFER_SIZE 256 150 151 #define CFG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ 152 153 #endif 154