1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __LS1043AQDS_H__ 7 #define __LS1043AQDS_H__ 8 9 #include "ls1043a_common.h" 10 11 /* Physical Memory Map */ 12 13 #define SPD_EEPROM_ADDRESS 0x51 14 15 #ifdef CONFIG_SYS_DPAA_FMAN 16 #define RGMII_PHY1_ADDR 0x1 17 #define RGMII_PHY2_ADDR 0x2 18 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 19 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 20 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 21 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 22 /* PHY address on QSGMII riser card on slot 1 */ 23 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 24 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 25 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 26 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 27 /* PHY address on QSGMII riser card on slot 2 */ 28 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 29 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 30 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 31 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 32 #endif 33 34 /* 35 * IFC Definitions 36 */ 37 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 38 #define CFG_SYS_NOR0_CSPR_EXT (0x0) 39 #define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ 40 CSPR_PORT_SIZE_16 | \ 41 CSPR_MSEL_NOR | \ 42 CSPR_V) 43 #define CFG_SYS_NOR1_CSPR_EXT (0x0) 44 #define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ 45 + 0x8000000) | \ 46 CSPR_PORT_SIZE_16 | \ 47 CSPR_MSEL_NOR | \ 48 CSPR_V) 49 #define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 50 51 #define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 52 CSOR_NOR_TRHZ_80) 53 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 54 FTIM0_NOR_TEADC(0x5) | \ 55 FTIM0_NOR_TEAHC(0x5)) 56 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 57 FTIM1_NOR_TRAD_NOR(0x1a) | \ 58 FTIM1_NOR_TSEQRAD_NOR(0x13)) 59 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 60 FTIM2_NOR_TCH(0x4) | \ 61 FTIM2_NOR_TWPH(0xe) | \ 62 FTIM2_NOR_TWP(0x1c)) 63 #define CFG_SYS_NOR_FTIM3 0 64 65 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ 66 CFG_SYS_FLASH_BASE_PHYS + 0x8000000} 67 68 #define CFG_SYS_WRITE_SWAPPED_DATA 69 70 /* 71 * NAND Flash Definitions 72 */ 73 74 #define CFG_SYS_NAND_BASE 0x7e800000 75 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE 76 77 #define CFG_SYS_NAND_CSPR_EXT (0x0) 78 79 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ 80 | CSPR_PORT_SIZE_8 \ 81 | CSPR_MSEL_NAND \ 82 | CSPR_V) 83 #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) 84 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 85 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 86 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 87 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 88 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 89 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 90 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 91 92 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 93 FTIM0_NAND_TWP(0x18) | \ 94 FTIM0_NAND_TWCHT(0x7) | \ 95 FTIM0_NAND_TWH(0xa)) 96 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 97 FTIM1_NAND_TWBE(0x39) | \ 98 FTIM1_NAND_TRR(0xe) | \ 99 FTIM1_NAND_TRP(0x18)) 100 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 101 FTIM2_NAND_TREH(0xa) | \ 102 FTIM2_NAND_TWHRE(0x1e)) 103 #define CFG_SYS_NAND_FTIM3 0x0 104 105 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 106 #endif 107 108 #ifdef CONFIG_NAND_BOOT 109 #define CFG_SYS_NAND_U_BOOT_SIZE (640 << 10) 110 #endif 111 112 #if defined(CONFIG_TFABOOT) || \ 113 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 114 #endif 115 116 /* 117 * QIXIS Definitions 118 */ 119 120 #ifdef CONFIG_FSL_QIXIS 121 #define QIXIS_BASE 0x7fb00000 122 #define QIXIS_BASE_PHYS QIXIS_BASE 123 #define CFG_SYS_I2C_FPGA_ADDR 0x66 124 #define QIXIS_LBMAP_SWITCH 6 125 #define QIXIS_LBMAP_MASK 0x0f 126 #define QIXIS_LBMAP_SHIFT 0 127 #define QIXIS_LBMAP_DFLTBANK 0x00 128 #define QIXIS_LBMAP_ALTBANK 0x04 129 #define QIXIS_LBMAP_NAND 0x09 130 #define QIXIS_LBMAP_SD 0x00 131 #define QIXIS_LBMAP_SD_QSPI 0xff 132 #define QIXIS_LBMAP_QSPI 0xff 133 #define QIXIS_RCW_SRC_NAND 0x106 134 #define QIXIS_RCW_SRC_SD 0x040 135 #define QIXIS_RCW_SRC_QSPI 0x045 136 #define QIXIS_RST_CTL_RESET 0x41 137 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 138 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 139 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 140 141 #define CFG_SYS_FPGA_CSPR_EXT (0x0) 142 #define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 143 CSPR_PORT_SIZE_8 | \ 144 CSPR_MSEL_GPCM | \ 145 CSPR_V) 146 #define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 147 #define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 148 CSOR_NOR_NOR_MODE_AVD_NOR | \ 149 CSOR_NOR_TRHZ_80) 150 151 /* 152 * QIXIS Timing parameters for IFC GPCM 153 */ 154 #define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 155 FTIM0_GPCM_TEADC(0x20) | \ 156 FTIM0_GPCM_TEAHC(0x10)) 157 #define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 158 FTIM1_GPCM_TRAD(0x1f)) 159 #define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 160 FTIM2_GPCM_TCH(0x8) | \ 161 FTIM2_GPCM_TWP(0xf0)) 162 #define CFG_SYS_FPGA_FTIM3 0x0 163 #endif 164 165 #ifdef CONFIG_TFABOOT 166 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT 167 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR 168 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK 169 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR 170 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 171 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 172 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 173 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 174 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT 175 #define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR 176 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK 177 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR 178 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 179 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 180 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 181 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 182 #define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT 183 #define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR 184 #define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK 185 #define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR 186 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 187 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 188 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 189 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 190 #define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT 191 #define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR 192 #define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK 193 #define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR 194 #define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 195 #define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 196 #define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 197 #define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 198 #else 199 #ifdef CONFIG_NAND_BOOT 200 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT 201 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR 202 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK 203 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR 204 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 205 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 206 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 207 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 208 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT 209 #define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR 210 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK 211 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR 212 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 213 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 214 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 215 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 216 #define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT 217 #define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR 218 #define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK 219 #define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR 220 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 221 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 222 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 223 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 224 #define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT 225 #define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR 226 #define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK 227 #define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR 228 #define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 229 #define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 230 #define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 231 #define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 232 #else 233 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT 234 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR 235 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK 236 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR 237 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 238 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 239 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 240 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 241 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT 242 #define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR 243 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK 244 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR 245 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 246 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 247 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 248 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 249 #define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT 250 #define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR 251 #define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK 252 #define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR 253 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 254 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 255 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 256 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 257 #define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT 258 #define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR 259 #define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK 260 #define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR 261 #define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 262 #define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 263 #define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 264 #define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 265 #endif 266 #endif 267 268 /* 269 * I2C bus multiplexer 270 */ 271 #define I2C_MUX_PCA_ADDR_PRI 0x77 272 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 273 #define I2C_RETIMER_ADDR 0x18 274 #define I2C_MUX_CH_DEFAULT 0x8 275 #define I2C_MUX_CH_CH7301 0xC 276 #define I2C_MUX_CH5 0xD 277 #define I2C_MUX_CH7 0xF 278 279 #define I2C_MUX_CH_VOL_MONITOR 0xa 280 281 /* Voltage monitor on channel 2*/ 282 #define I2C_VOL_MONITOR_ADDR 0x40 283 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 284 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 285 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 286 287 /* The lowest and highest voltage allowed for LS1043AQDS */ 288 #define VDD_MV_MIN 819 289 #define VDD_MV_MAX 1212 290 291 /* 292 * Miscellaneous configurable options 293 */ 294 295 /* 296 * Environment 297 */ 298 299 #include <asm/fsl_secure_boot.h> 300 301 #endif /* __LS1043AQDS_H__ */ 302