1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015 Freescale Semiconductor 4 * Copyright 2022 NXP 5 */ 6 7 #ifndef __LS1043ARDB_H__ 8 #define __LS1043ARDB_H__ 9 10 #include "ls1043a_common.h" 11 12 /* 13 * NOR Flash Definitions 14 */ 15 #define CFG_SYS_NOR_CSPR_EXT (0x0) 16 #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 17 #define CFG_SYS_NOR_CSPR \ 18 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ 19 CSPR_PORT_SIZE_16 | \ 20 CSPR_MSEL_NOR | \ 21 CSPR_V) 22 23 /* NOR Flash Timing Params */ 24 #define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 25 CSOR_NOR_TRHZ_80) 26 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 27 FTIM0_NOR_TEADC(0x1) | \ 28 FTIM0_NOR_TAVDS(0x0) | \ 29 FTIM0_NOR_TEAHC(0xc)) 30 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ 31 FTIM1_NOR_TRAD_NOR(0xb) | \ 32 FTIM1_NOR_TSEQRAD_NOR(0x9)) 33 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ 34 FTIM2_NOR_TCH(0x4) | \ 35 FTIM2_NOR_TWPH(0x8) | \ 36 FTIM2_NOR_TWP(0x10)) 37 #define CFG_SYS_NOR_FTIM3 0 38 #define CFG_SYS_IFC_CCR 0x01000000 39 40 #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } 41 42 #define CFG_SYS_WRITE_SWAPPED_DATA 43 44 /* 45 * NAND Flash Definitions 46 */ 47 48 #define CFG_SYS_NAND_BASE 0x7e800000 49 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE 50 51 #define CFG_SYS_NAND_CSPR_EXT (0x0) 52 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ 53 | CSPR_PORT_SIZE_8 \ 54 | CSPR_MSEL_NAND \ 55 | CSPR_V) 56 #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) 57 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 58 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 59 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 60 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 61 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 62 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 63 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 64 65 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 66 FTIM0_NAND_TWP(0x18) | \ 67 FTIM0_NAND_TWCHT(0x7) | \ 68 FTIM0_NAND_TWH(0xa)) 69 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 70 FTIM1_NAND_TWBE(0x39) | \ 71 FTIM1_NAND_TRR(0xe) | \ 72 FTIM1_NAND_TRP(0x18)) 73 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 74 FTIM2_NAND_TREH(0xa) | \ 75 FTIM2_NAND_TWHRE(0x1e)) 76 #define CFG_SYS_NAND_FTIM3 0x0 77 78 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 79 80 #ifdef CONFIG_NAND_BOOT 81 #define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10) 82 #endif 83 84 /* 85 * CPLD 86 */ 87 #define CFG_SYS_CPLD_BASE 0x7fb00000 88 #define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE 89 90 #define CFG_SYS_CPLD_CSPR_EXT (0x0) 91 #define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 92 CSPR_PORT_SIZE_8 | \ 93 CSPR_MSEL_GPCM | \ 94 CSPR_V) 95 #define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 96 #define CFG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 97 CSOR_NOR_NOR_MODE_AVD_NOR | \ 98 CSOR_NOR_TRHZ_80) 99 100 /* CPLD Timing parameters for IFC GPCM */ 101 #define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 102 FTIM0_GPCM_TEADC(0xf) | \ 103 FTIM0_GPCM_TEAHC(0xf)) 104 #define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 105 FTIM1_GPCM_TRAD(0x3f)) 106 #define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 107 FTIM2_GPCM_TCH(0xf) | \ 108 FTIM2_GPCM_TWP(0xff)) 109 #define CFG_SYS_CPLD_FTIM3 0x0 110 111 /* IFC Timing Params */ 112 #ifdef CONFIG_TFABOOT 113 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT 114 #define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR 115 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK 116 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR 117 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 118 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 119 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 120 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 121 122 #define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT 123 #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR 124 #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK 125 #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR 126 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 127 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 128 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 129 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 130 #else 131 #ifdef CONFIG_NAND_BOOT 132 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT 133 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR 134 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK 135 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR 136 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 137 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 138 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 139 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 140 141 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT 142 #define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR 143 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK 144 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR 145 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 146 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 147 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 148 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 149 #else 150 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT 151 #define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR 152 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK 153 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR 154 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 155 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 156 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 157 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 158 159 #define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT 160 #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR 161 #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK 162 #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR 163 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 164 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 165 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 166 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 167 #endif 168 #endif 169 170 #define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT 171 #define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR 172 #define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK 173 #define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR 174 #define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0 175 #define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1 176 #define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2 177 #define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3 178 179 /* 180 * Environment 181 */ 182 183 /* FMan */ 184 #ifndef SPL_NO_FMAN 185 #define AQR105_IRQ_MASK 0x40000000 186 187 #ifdef CONFIG_SYS_DPAA_FMAN 188 #define RGMII_PHY1_ADDR 0x1 189 #define RGMII_PHY2_ADDR 0x2 190 191 #define QSGMII_PORT1_PHY_ADDR 0x4 192 #define QSGMII_PORT2_PHY_ADDR 0x5 193 #define QSGMII_PORT3_PHY_ADDR 0x6 194 #define QSGMII_PORT4_PHY_ADDR 0x7 195 196 /* The AQR PHY model and MDIO address differ between board revisions */ 197 #define FM1_10GEC1_PHY_ADDR 0x1 /* AQR105 on boards up to v6.0 */ 198 #define AQR113C_PHY_ADDR 0x8 /* AQR113C on boards v7.0 and up */ 199 #endif 200 #endif 201 202 #include <asm/fsl_secure_boot.h> 203 204 #endif /* __LS1043ARDB_H__ */ 205