1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor 4 * Copyright 2019 NXP 5 */ 6 7 #ifndef __LS1046ARDB_H__ 8 #define __LS1046ARDB_H__ 9 10 #include "ls1046a_common.h" 11 12 /* Physical Memory Map */ 13 14 #define SPD_EEPROM_ADDRESS 0x51 15 16 #if defined(CONFIG_QSPI_BOOT) 17 #define CFG_SYS_UBOOT_BASE 0x40100000 18 #endif 19 20 #define CFG_SYS_NAND_BASE 0x7e800000 21 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE 22 23 #define CFG_SYS_NAND_CSPR_EXT (0x0) 24 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ 25 | CSPR_PORT_SIZE_8 \ 26 | CSPR_MSEL_NAND \ 27 | CSPR_V) 28 #define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 29 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 30 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 31 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 32 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 33 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 34 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 35 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 36 37 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 38 FTIM0_NAND_TWP(0x18) | \ 39 FTIM0_NAND_TWCHT(0x7) | \ 40 FTIM0_NAND_TWH(0xa)) 41 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 42 FTIM1_NAND_TWBE(0x39) | \ 43 FTIM1_NAND_TRR(0xe) | \ 44 FTIM1_NAND_TRP(0x18)) 45 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 46 FTIM2_NAND_TREH(0xa) | \ 47 FTIM2_NAND_TWHRE(0x1e)) 48 #define CFG_SYS_NAND_FTIM3 0x0 49 50 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 51 52 /* 53 * CPLD 54 */ 55 #define CFG_SYS_CPLD_BASE 0x7fb00000 56 #define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE 57 58 #define CFG_SYS_CPLD_CSPR_EXT (0x0) 59 #define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 60 CSPR_PORT_SIZE_8 | \ 61 CSPR_MSEL_GPCM | \ 62 CSPR_V) 63 #define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 64 #define CFG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) 65 66 /* CPLD Timing parameters for IFC GPCM */ 67 #define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 68 FTIM0_GPCM_TEADC(0x0e) | \ 69 FTIM0_GPCM_TEAHC(0x0e)) 70 #define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 71 FTIM1_GPCM_TRAD(0x3f)) 72 #define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 73 FTIM2_GPCM_TCH(0xf) | \ 74 FTIM2_GPCM_TWP(0x3E)) 75 #define CFG_SYS_CPLD_FTIM3 0x0 76 77 /* IFC Timing Params */ 78 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT 79 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR 80 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK 81 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR 82 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 83 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 84 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 85 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 86 87 #define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT 88 #define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR 89 #define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK 90 #define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR 91 #define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0 92 #define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1 93 #define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2 94 #define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3 95 96 /* EEPROM */ 97 #define I2C_RETIMER_ADDR 0x18 98 99 /* PMIC */ 100 101 /* 102 * Environment 103 */ 104 #define CFG_SYS_FSL_QSPI_BASE 0x40000000 105 106 #define AQR105_IRQ_MASK 0x80000000 107 /* FMan */ 108 #ifndef SPL_NO_FMAN 109 #ifdef CONFIG_SYS_DPAA_FMAN 110 #define RGMII_PHY1_ADDR 0x1 111 #define RGMII_PHY2_ADDR 0x2 112 113 #define SGMII_PHY1_ADDR 0x3 114 #define SGMII_PHY2_ADDR 0x4 115 116 #define FM1_10GEC1_PHY_ADDR 0x0 117 118 #define FDT_SEQ_MACADDR_FROM_ENV 119 #endif 120 121 #endif 122 123 #ifndef SPL_NO_MISC 124 #ifdef CONFIG_TFABOOT 125 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 126 "env exists secureboot && esbc_halt;;" 127 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ 128 "env exists secureboot && esbc_halt;" 129 #endif 130 #endif 131 132 #include <asm/fsl_secure_boot.h> 133 134 #endif /* __LS1046ARDB_H__ */ 135