1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017, 2020-2021 NXP 4 */ 5 6 #ifndef __LS1088A_RDB_H 7 #define __LS1088A_RDB_H 8 9 #include "ls1088a_common.h" 10 11 #if defined(CONFIG_TFABOOT) || \ 12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 13 #define SYS_NO_FLASH 14 #endif 15 16 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ 17 18 #define SPD_EEPROM_ADDRESS 0x51 19 20 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 21 #define CFG_SYS_NOR0_CSPR_EXT (0x0) 22 #define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 23 #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) 24 25 #define CFG_SYS_NOR0_CSPR \ 26 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ 27 CSPR_PORT_SIZE_16 | \ 28 CSPR_MSEL_NOR | \ 29 CSPR_V) 30 #define CFG_SYS_NOR0_CSPR_EARLY \ 31 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ 32 CSPR_PORT_SIZE_16 | \ 33 CSPR_MSEL_NOR | \ 34 CSPR_V) 35 #define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) 36 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 37 FTIM0_NOR_TEADC(0x1) | \ 38 FTIM0_NOR_TEAHC(0x1)) 39 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 40 FTIM1_NOR_TRAD_NOR(0x1)) 41 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 42 FTIM2_NOR_TCH(0x0) | \ 43 FTIM2_NOR_TWP(0x1)) 44 #define CFG_SYS_NOR_FTIM3 0x04000000 45 #define CFG_SYS_IFC_CCR 0x01000000 46 47 #ifndef SYS_NO_FLASH 48 #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } 49 #endif 50 #endif 51 52 #define CFG_SYS_NAND_CSPR_EXT (0x0) 53 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ 54 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 55 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 56 | CSPR_V) 57 #define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 58 59 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 60 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 61 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 62 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 63 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 64 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 65 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 66 67 /* ONFI NAND Flash mode0 Timing Params */ 68 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 69 FTIM0_NAND_TWP(0x18) | \ 70 FTIM0_NAND_TWCHT(0x07) | \ 71 FTIM0_NAND_TWH(0x0a)) 72 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 73 FTIM1_NAND_TWBE(0x39) | \ 74 FTIM1_NAND_TRR(0x0e) | \ 75 FTIM1_NAND_TRP(0x18)) 76 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 77 FTIM2_NAND_TREH(0x0a) | \ 78 FTIM2_NAND_TWHRE(0x1e)) 79 #define CFG_SYS_NAND_FTIM3 0x0 80 81 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 82 83 #define CFG_SYS_I2C_FPGA_ADDR 0x66 84 #define QIXIS_BRDCFG4_OFFSET 0x54 85 #define QIXIS_LBMAP_SWITCH 2 86 #define QIXIS_QMAP_MASK 0xe0 87 #define QIXIS_QMAP_SHIFT 5 88 #define QIXIS_LBMAP_MASK 0x1f 89 #define QIXIS_LBMAP_SHIFT 5 90 #define QIXIS_LBMAP_DFLTBANK 0x00 91 #define QIXIS_LBMAP_ALTBANK 0x20 92 #define QIXIS_LBMAP_SD 0x00 93 #define QIXIS_LBMAP_EMMC 0x00 94 #define QIXIS_LBMAP_SD_QSPI 0x00 95 #define QIXIS_LBMAP_QSPI 0x00 96 #define QIXIS_RCW_SRC_SD 0x40 97 #define QIXIS_RCW_SRC_EMMC 0x41 98 #define QIXIS_RCW_SRC_QSPI 0x62 99 #define QIXIS_RST_CTL_RESET 0x31 100 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 101 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 102 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 103 #define QIXIS_RST_FORCE_MEM 0x01 104 105 #define CFG_SYS_FPGA_CSPR_EXT (0x0) 106 #define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 107 | CSPR_PORT_SIZE_8 \ 108 | CSPR_MSEL_GPCM \ 109 | CSPR_V) 110 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 111 | CSPR_PORT_SIZE_8 \ 112 | CSPR_MSEL_GPCM \ 113 | CSPR_V) 114 115 #define CFG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 116 #define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 117 /* QIXIS Timing parameters*/ 118 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 119 FTIM0_GPCM_TEADC(0x0e) | \ 120 FTIM0_GPCM_TEAHC(0x0e)) 121 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 122 FTIM1_GPCM_TRAD(0x3f)) 123 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 124 FTIM2_GPCM_TCH(0xf) | \ 125 FTIM2_GPCM_TWP(0x3E)) 126 #define SYS_FPGA_CS_FTIM3 0x0 127 128 #if defined(CONFIG_TFABOOT) || \ 129 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 130 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT 131 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR 132 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK 133 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR 134 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 135 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 136 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 137 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 138 #define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT 139 #define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR 140 #define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 141 #define CFG_SYS_AMASK2 CFG_SYS_FPGA_AMASK 142 #define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR 143 #define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 144 #define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 145 #define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 146 #define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 147 #else 148 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT 149 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY 150 #define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR 151 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK 152 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR 153 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 154 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 155 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 156 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 157 #endif 158 159 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 160 161 #define I2C_MUX_CH_VOL_MONITOR 0xA 162 /* Voltage monitor on channel 2*/ 163 #define I2C_VOL_MONITOR_ADDR 0x63 164 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 165 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 166 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 167 #define I2C_SVDD_MONITOR_ADDR 0x4F 168 169 /* The lowest and highest voltage allowed for LS1088ARDB */ 170 #define VDD_MV_MIN 819 171 #define VDD_MV_MAX 1212 172 173 #define PWM_CHANNEL0 0x0 174 175 /* 176 * I2C bus multiplexer 177 */ 178 #define I2C_MUX_PCA_ADDR_PRI 0x77 179 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 180 #define I2C_RETIMER_ADDR 0x18 181 #define I2C_MUX_CH_DEFAULT 0x8 182 #define I2C_MUX_CH5 0xD 183 184 /* 185 * RTC configuration 186 */ 187 #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 188 189 #ifndef SPL_NO_ENV 190 /* Initial environment variables */ 191 #ifdef CONFIG_TFABOOT 192 #define QSPI_MC_INIT_CMD \ 193 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \ 194 "sf read 0x80e00000 0xE00000 0x100000;" \ 195 "env exists secureboot && " \ 196 "sf read 0x80640000 0x640000 0x40000 && " \ 197 "sf read 0x80680000 0x680000 0x40000 && " \ 198 "esbc_validate 0x80640000 && " \ 199 "esbc_validate 0x80680000 ;" \ 200 "fsl_mc start mc 0x80a00000 0x80e00000\0" 201 #define SD_MC_INIT_CMD \ 202 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \ 203 "mmc read 0x80e00000 0x7000 0x800;" \ 204 "env exists secureboot && " \ 205 "mmc read 0x80640000 0x3200 0x20 && " \ 206 "mmc read 0x80680000 0x3400 0x20 && " \ 207 "esbc_validate 0x80640000 && " \ 208 "esbc_validate 0x80680000 ;" \ 209 "fsl_mc start mc 0x80a00000 0x80e00000\0" 210 #else 211 #if defined(CONFIG_QSPI_BOOT) 212 #define MC_INIT_CMD \ 213 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \ 214 "sf read 0x80e00000 0xE00000 0x100000;" \ 215 "env exists secureboot && " \ 216 "sf read 0x80640000 0x640000 0x40000 && " \ 217 "sf read 0x80680000 0x680000 0x40000 && " \ 218 "esbc_validate 0x80640000 && " \ 219 "esbc_validate 0x80680000 ;" \ 220 "fsl_mc start mc 0x80a00000 0x80e00000\0" \ 221 "mcmemsize=0x70000000\0" 222 #elif defined(CONFIG_SD_BOOT) 223 #define MC_INIT_CMD \ 224 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \ 225 "mmc read 0x80e00000 0x7000 0x800;" \ 226 "env exists secureboot && " \ 227 "mmc read 0x80640000 0x3200 0x20 && " \ 228 "mmc read 0x80680000 0x3400 0x20 && " \ 229 "esbc_validate 0x80640000 && " \ 230 "esbc_validate 0x80680000 ;" \ 231 "fsl_mc start mc 0x80a00000 0x80e00000\0" \ 232 "mcmemsize=0x70000000\0" 233 #endif 234 #endif /* CONFIG_TFABOOT */ 235 236 #undef CFG_EXTRA_ENV_SETTINGS 237 #ifdef CONFIG_TFABOOT 238 #define CFG_EXTRA_ENV_SETTINGS \ 239 "BOARD=ls1088ardb\0" \ 240 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 241 "ramdisk_addr=0x800000\0" \ 242 "ramdisk_size=0x2000000\0" \ 243 "fdt_high=0xa0000000\0" \ 244 "initrd_high=0xffffffffffffffff\0" \ 245 "kernel_addr=0x1000000\0" \ 246 "kernel_addr_sd=0x8000\0" \ 247 "kernelhdr_addr_sd=0x3000\0" \ 248 "kernel_start=0x580100000\0" \ 249 "kernelheader_start=0x580600000\0" \ 250 "scriptaddr=0x80000000\0" \ 251 "scripthdraddr=0x80080000\0" \ 252 "fdtheader_addr_r=0x80100000\0" \ 253 "kernelheader_addr=0x600000\0" \ 254 "kernelheader_addr_r=0x80200000\0" \ 255 "kernel_addr_r=0x81000000\0" \ 256 "kernelheader_size=0x40000\0" \ 257 "fdt_addr_r=0x90000000\0" \ 258 "load_addr=0xa0000000\0" \ 259 "kernel_size=0x2800000\0" \ 260 "kernel_size_sd=0x14000\0" \ 261 "kernelhdr_size_sd=0x20\0" \ 262 QSPI_MC_INIT_CMD \ 263 "mcmemsize=0x70000000\0" \ 264 BOOTENV \ 265 "boot_scripts=ls1088ardb_boot.scr\0" \ 266 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ 267 "scan_dev_for_boot_part=" \ 268 "part list ${devtype} ${devnum} devplist; " \ 269 "env exists devplist || setenv devplist 1; " \ 270 "for distro_bootpart in ${devplist}; do " \ 271 "if fstype ${devtype} " \ 272 "${devnum}:${distro_bootpart} " \ 273 "bootfstype; then " \ 274 "run scan_dev_for_boot; " \ 275 "fi; " \ 276 "done\0" \ 277 "boot_a_script=" \ 278 "load ${devtype} ${devnum}:${distro_bootpart} " \ 279 "${scriptaddr} ${prefix}${script}; " \ 280 "env exists secureboot && load ${devtype} " \ 281 "${devnum}:${distro_bootpart} " \ 282 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\ 283 "env exists secureboot " \ 284 "&& esbc_validate ${scripthdraddr};" \ 285 "source ${scriptaddr}\0" \ 286 "installer=load mmc 0:2 $load_addr " \ 287 "/flex_installer_arm64.itb; " \ 288 "env exists mcinitcmd && run mcinitcmd && " \ 289 "mmc read 0x80001000 0x6800 0x800;" \ 290 "fsl_mc lazyapply dpl 0x80001000;" \ 291 "bootm $load_addr#ls1088ardb\0" \ 292 "qspi_bootcmd=echo Trying load from qspi..;" \ 293 "sf probe && sf read $load_addr " \ 294 "$kernel_addr $kernel_size ; env exists secureboot " \ 295 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 296 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 297 "bootm $load_addr#$BOARD\0" \ 298 "sd_bootcmd=echo Trying load from sd card..;" \ 299 "mmcinfo; mmc read $load_addr " \ 300 "$kernel_addr_sd $kernel_size_sd ;" \ 301 "env exists secureboot && mmc read $kernelheader_addr_r "\ 302 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 303 " && esbc_validate ${kernelheader_addr_r};" \ 304 "bootm $load_addr#$BOARD\0" 305 #else 306 #define CFG_EXTRA_ENV_SETTINGS \ 307 "BOARD=ls1088ardb\0" \ 308 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 309 "ramdisk_addr=0x800000\0" \ 310 "ramdisk_size=0x2000000\0" \ 311 "fdt_high=0xa0000000\0" \ 312 "initrd_high=0xffffffffffffffff\0" \ 313 "kernel_addr=0x1000000\0" \ 314 "kernel_addr_sd=0x8000\0" \ 315 "kernelhdr_addr_sd=0x3000\0" \ 316 "kernel_start=0x580100000\0" \ 317 "kernelheader_start=0x580800000\0" \ 318 "scriptaddr=0x80000000\0" \ 319 "scripthdraddr=0x80080000\0" \ 320 "fdtheader_addr_r=0x80100000\0" \ 321 "kernelheader_addr=0x600000\0" \ 322 "kernelheader_addr_r=0x80200000\0" \ 323 "kernel_addr_r=0x81000000\0" \ 324 "kernelheader_size=0x40000\0" \ 325 "fdt_addr_r=0x90000000\0" \ 326 "load_addr=0xa0000000\0" \ 327 "kernel_size=0x2800000\0" \ 328 "kernel_size_sd=0x14000\0" \ 329 "kernelhdr_size_sd=0x20\0" \ 330 MC_INIT_CMD \ 331 BOOTENV \ 332 "boot_scripts=ls1088ardb_boot.scr\0" \ 333 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ 334 "scan_dev_for_boot_part=" \ 335 "part list ${devtype} ${devnum} devplist; " \ 336 "env exists devplist || setenv devplist 1; " \ 337 "for distro_bootpart in ${devplist}; do " \ 338 "if fstype ${devtype} " \ 339 "${devnum}:${distro_bootpart} " \ 340 "bootfstype; then " \ 341 "run scan_dev_for_boot; " \ 342 "fi; " \ 343 "done\0" \ 344 "boot_a_script=" \ 345 "load ${devtype} ${devnum}:${distro_bootpart} " \ 346 "${scriptaddr} ${prefix}${script}; " \ 347 "env exists secureboot && load ${devtype} " \ 348 "${devnum}:${distro_bootpart} " \ 349 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 350 "&& esbc_validate ${scripthdraddr};" \ 351 "source ${scriptaddr}\0" \ 352 "installer=load mmc 0:2 $load_addr " \ 353 "/flex_installer_arm64.itb; " \ 354 "env exists mcinitcmd && run mcinitcmd && " \ 355 "mmc read 0x80001000 0x6800 0x800;" \ 356 "fsl_mc lazyapply dpl 0x80001000;" \ 357 "bootm $load_addr#ls1088ardb\0" \ 358 "qspi_bootcmd=echo Trying load from qspi..;" \ 359 "sf probe && sf read $load_addr " \ 360 "$kernel_addr $kernel_size ; env exists secureboot " \ 361 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 362 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 363 "bootm $load_addr#$BOARD\0" \ 364 "sd_bootcmd=echo Trying load from sd card..;" \ 365 "mmcinfo; mmc read $load_addr " \ 366 "$kernel_addr_sd $kernel_size_sd ;" \ 367 "env exists secureboot && mmc read $kernelheader_addr_r "\ 368 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 369 " && esbc_validate ${kernelheader_addr_r};" \ 370 "bootm $load_addr#$BOARD\0" 371 #endif /* CONFIG_TFABOOT */ 372 373 #ifdef CONFIG_TFABOOT 374 #define QSPI_NOR_BOOTCOMMAND \ 375 "sf read 0x80001000 0xd00000 0x100000;" \ 376 "env exists mcinitcmd && env exists secureboot " \ 377 " && sf read 0x806C0000 0x6C0000 0x100000 " \ 378 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ 379 "&& fsl_mc lazyapply dpl 0x80001000;" \ 380 "run distro_bootcmd;run qspi_bootcmd;" \ 381 "env exists secureboot && esbc_halt;" 382 #define SD_BOOTCOMMAND \ 383 "env exists mcinitcmd && mmcinfo; " \ 384 "mmc read 0x80001000 0x6800 0x800; " \ 385 "env exists mcinitcmd && env exists secureboot " \ 386 " && mmc read 0x806C0000 0x3600 0x20 " \ 387 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ 388 "&& fsl_mc lazyapply dpl 0x80001000;" \ 389 "run distro_bootcmd;run sd_bootcmd;" \ 390 "env exists secureboot && esbc_halt;" 391 #else 392 #if defined(CONFIG_QSPI_BOOT) 393 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 394 395 /* Try to boot an on-SD kernel first, then do normal distro boot */ 396 #endif 397 #endif /* CONFIG_TFABOOT */ 398 399 /* MAC/PHY configuration */ 400 #ifdef CONFIG_FSL_MC_ENET 401 #define AQ_PHY_ADDR1 0x00 402 #define AQR105_IRQ_MASK 0x00000004 403 404 #define QSGMII1_PORT1_PHY_ADDR 0x0c 405 #define QSGMII1_PORT2_PHY_ADDR 0x0d 406 #define QSGMII1_PORT3_PHY_ADDR 0x0e 407 #define QSGMII1_PORT4_PHY_ADDR 0x0f 408 #define QSGMII2_PORT1_PHY_ADDR 0x1c 409 #define QSGMII2_PORT2_PHY_ADDR 0x1d 410 #define QSGMII2_PORT3_PHY_ADDR 0x1e 411 #define QSGMII2_PORT4_PHY_ADDR 0x1f 412 #endif 413 #endif 414 415 #ifndef SPL_NO_ENV 416 417 #define BOOT_TARGET_DEVICES(func) \ 418 func(MMC, mmc, 0) \ 419 func(USB, usb, 0) \ 420 func(SCSI, scsi, 0) \ 421 func(DHCP, dhcp, na) 422 #include <config_distro_bootcmd.h> 423 #endif 424 425 #include <asm/fsl_secure_boot.h> 426 427 #endif /* __LS1088A_RDB_H */ 428