1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017, 2019-2021 NXP 4 * Copyright 2015 Freescale Semiconductor 5 */ 6 7 #ifndef __LS2_QDS_H 8 #define __LS2_QDS_H 9 10 #include "ls2080a_common.h" 11 12 #ifdef CONFIG_FSL_QSPI 13 #define CFG_SYS_I2C_IFDR_DIV 0x7e 14 #endif 15 16 #define CFG_SYS_I2C_FPGA_ADDR 0x66 17 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) 18 19 #define SPD_EEPROM_ADDRESS1 0x51 20 #define SPD_EEPROM_ADDRESS2 0x52 21 #define SPD_EEPROM_ADDRESS3 0x53 22 #define SPD_EEPROM_ADDRESS4 0x54 23 #define SPD_EEPROM_ADDRESS5 0x55 24 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 25 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 26 27 #define CFG_SYS_NOR0_CSPR_EXT (0x0) 28 #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 29 #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 30 31 #define CFG_SYS_NOR0_CSPR \ 32 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ 33 CSPR_PORT_SIZE_16 | \ 34 CSPR_MSEL_NOR | \ 35 CSPR_V) 36 #define CFG_SYS_NOR0_CSPR_EARLY \ 37 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ 38 CSPR_PORT_SIZE_16 | \ 39 CSPR_MSEL_NOR | \ 40 CSPR_V) 41 #define CFG_SYS_NOR1_CSPR \ 42 (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \ 43 CSPR_PORT_SIZE_16 | \ 44 CSPR_MSEL_NOR | \ 45 CSPR_V) 46 #define CFG_SYS_NOR1_CSPR_EARLY \ 47 (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 48 CSPR_PORT_SIZE_16 | \ 49 CSPR_MSEL_NOR | \ 50 CSPR_V) 51 #define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 52 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 53 FTIM0_NOR_TEADC(0x5) | \ 54 FTIM0_NOR_TEAHC(0x5)) 55 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 56 FTIM1_NOR_TRAD_NOR(0x1a) |\ 57 FTIM1_NOR_TSEQRAD_NOR(0x13)) 58 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 59 FTIM2_NOR_TCH(0x4) | \ 60 FTIM2_NOR_TWPH(0x0E) | \ 61 FTIM2_NOR_TWP(0x1c)) 62 #define CFG_SYS_NOR_FTIM3 0x04000000 63 #define CFG_SYS_IFC_CCR 0x01000000 64 65 #ifdef CONFIG_MTD_NOR_FLASH 66 #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ 67 CFG_SYS_FLASH_BASE + 0x40000000} 68 #endif 69 70 #define CFG_SYS_NAND_CSPR_EXT (0x0) 71 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ 72 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 73 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 74 | CSPR_V) 75 #define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 76 77 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 78 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 79 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 80 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 81 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 82 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 83 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 84 85 /* ONFI NAND Flash mode0 Timing Params */ 86 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 87 FTIM0_NAND_TWP(0x18) | \ 88 FTIM0_NAND_TWCHT(0x07) | \ 89 FTIM0_NAND_TWH(0x0a)) 90 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 91 FTIM1_NAND_TWBE(0x39) | \ 92 FTIM1_NAND_TRR(0x0e) | \ 93 FTIM1_NAND_TRP(0x18)) 94 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 95 FTIM2_NAND_TREH(0x0a) | \ 96 FTIM2_NAND_TWHRE(0x1e)) 97 #define CFG_SYS_NAND_FTIM3 0x0 98 99 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 100 101 #define QIXIS_LBMAP_SWITCH 0x06 102 #define QIXIS_LBMAP_MASK 0x0f 103 #define QIXIS_LBMAP_SHIFT 0 104 #define QIXIS_LBMAP_DFLTBANK 0x00 105 #define QIXIS_LBMAP_ALTBANK 0x04 106 #define QIXIS_LBMAP_NAND 0x09 107 #define QIXIS_LBMAP_SD 0x00 108 #define QIXIS_LBMAP_QSPI 0x0f 109 #define QIXIS_RST_CTL_RESET 0x31 110 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 111 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 112 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 113 #define QIXIS_RCW_SRC_NAND 0x107 114 #define QIXIS_RCW_SRC_SD 0x40 115 #define QIXIS_RCW_SRC_QSPI 0x62 116 #define QIXIS_RST_FORCE_MEM 0x01 117 118 #define CFG_SYS_CSPR3_EXT (0x0) 119 #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 120 | CSPR_PORT_SIZE_8 \ 121 | CSPR_MSEL_GPCM \ 122 | CSPR_V) 123 #define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 124 | CSPR_PORT_SIZE_8 \ 125 | CSPR_MSEL_GPCM \ 126 | CSPR_V) 127 128 #define CFG_SYS_AMASK3 IFC_AMASK(64*1024) 129 #define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 130 /* QIXIS Timing parameters for IFC CS3 */ 131 #define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 132 FTIM0_GPCM_TEADC(0x0e) | \ 133 FTIM0_GPCM_TEAHC(0x0e)) 134 #define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 135 FTIM1_GPCM_TRAD(0x3f)) 136 #define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 137 FTIM2_GPCM_TCH(0xf) | \ 138 FTIM2_GPCM_TWP(0x3E)) 139 #define CFG_SYS_CS3_FTIM3 0x0 140 141 #if defined(CONFIG_SPL) 142 #if defined(CONFIG_NAND_BOOT) 143 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT 144 #define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR_EARLY 145 #define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR0_CSPR 146 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK 147 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR 148 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 149 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 150 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 151 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 152 #define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT 153 #define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR_EARLY 154 #define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR1_CSPR 155 #define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY 156 #define CFG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK 157 #define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR 158 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 159 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 160 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 161 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 162 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT 163 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR 164 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK 165 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR 166 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 167 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 168 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 169 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 170 171 #define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 172 #endif 173 #else 174 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT 175 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY 176 #define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR 177 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK 178 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR 179 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 180 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 181 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 182 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 183 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT 184 #define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY 185 #define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR 186 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY 187 #define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK 188 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR 189 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 190 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 191 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 192 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 193 #define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT 194 #define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR 195 #define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK 196 #define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR 197 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 198 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 199 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 200 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 201 #endif 202 203 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 204 205 /* 206 * I2C 207 */ 208 #define I2C_MUX_PCA_ADDR 0x77 209 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 210 211 /* I2C bus multiplexer */ 212 #define I2C_MUX_CH_DEFAULT 0x8 213 214 /* SPI */ 215 216 /* 217 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 218 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 219 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 220 */ 221 #define FSL_QIXIS_BRDCFG9_QSPI 0x1 222 223 /* 224 * RTC configuration 225 */ 226 #define CFG_SYS_I2C_RTC_ADDR 0x68 227 228 /* Initial environment variables */ 229 #undef CFG_EXTRA_ENV_SETTINGS 230 #ifdef CONFIG_NXP_ESBC 231 #define CFG_EXTRA_ENV_SETTINGS \ 232 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 233 "loadaddr=0x80100000\0" \ 234 "kernel_addr=0x100000\0" \ 235 "ramdisk_addr=0x800000\0" \ 236 "ramdisk_size=0x2000000\0" \ 237 "fdt_high=0xa0000000\0" \ 238 "initrd_high=0xffffffffffffffff\0" \ 239 "kernel_start=0x581000000\0" \ 240 "kernel_load=0xa0000000\0" \ 241 "kernel_size=0x2800000\0" \ 242 "mcmemsize=0x40000000\0" \ 243 "mcinitcmd=esbc_validate 0x580640000;" \ 244 "esbc_validate 0x580680000;" \ 245 "fsl_mc start mc 0x580a00000" \ 246 " 0x580e00000 \0" 247 #else 248 #ifdef CONFIG_TFABOOT 249 #define SD_MC_INIT_CMD \ 250 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \ 251 "mmc read 0x80e00000 0x7000 0x800;" \ 252 "fsl_mc start mc 0x80a00000 0x80e00000\0" 253 #define IFC_MC_INIT_CMD \ 254 "fsl_mc start mc 0x580a00000" \ 255 " 0x580e00000 \0" 256 #define CFG_EXTRA_ENV_SETTINGS \ 257 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 258 "loadaddr=0x80100000\0" \ 259 "loadaddr_sd=0x90100000\0" \ 260 "kernel_addr=0x581000000\0" \ 261 "kernel_addr_sd=0x8000\0" \ 262 "ramdisk_addr=0x800000\0" \ 263 "ramdisk_size=0x2000000\0" \ 264 "fdt_high=0xa0000000\0" \ 265 "initrd_high=0xffffffffffffffff\0" \ 266 "kernel_start=0x581000000\0" \ 267 "kernel_start_sd=0x8000\0" \ 268 "kernel_load=0xa0000000\0" \ 269 "kernel_size=0x2800000\0" \ 270 "kernel_size_sd=0x14000\0" \ 271 "load_addr=0xa0000000\0" \ 272 "kernelheader_addr=0x580600000\0" \ 273 "kernelheader_addr_r=0x80200000\0" \ 274 "kernelheader_size=0x40000\0" \ 275 "BOARD=ls2088aqds\0" \ 276 "mcmemsize=0x70000000 \0" \ 277 "scriptaddr=0x80000000\0" \ 278 "scripthdraddr=0x80080000\0" \ 279 IFC_MC_INIT_CMD \ 280 BOOTENV \ 281 "boot_scripts=ls2088aqds_boot.scr\0" \ 282 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \ 283 "scan_dev_for_boot_part=" \ 284 "part list ${devtype} ${devnum} devplist; " \ 285 "env exists devplist || setenv devplist 1; " \ 286 "for distro_bootpart in ${devplist}; do " \ 287 "if fstype ${devtype} " \ 288 "${devnum}:${distro_bootpart} " \ 289 "bootfstype; then " \ 290 "run scan_dev_for_boot; " \ 291 "fi; " \ 292 "done\0" \ 293 "boot_a_script=" \ 294 "load ${devtype} ${devnum}:${distro_bootpart} " \ 295 "${scriptaddr} ${prefix}${script}; " \ 296 "env exists secureboot && load ${devtype} " \ 297 "${devnum}:${distro_bootpart} " \ 298 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 299 "&& esbc_validate ${scripthdraddr};" \ 300 "source ${scriptaddr}\0" \ 301 "nor_bootcmd=echo Trying load from nor..;" \ 302 "cp.b $kernel_addr $load_addr " \ 303 "$kernel_size ; env exists secureboot && " \ 304 "cp.b $kernelheader_addr $kernelheader_addr_r " \ 305 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 306 "bootm $load_addr#$BOARD\0" \ 307 "sd_bootcmd=echo Trying load from SD ..;" \ 308 "mmcinfo; mmc read $load_addr " \ 309 "$kernel_addr_sd $kernel_size_sd && " \ 310 "bootm $load_addr#$BOARD\0" 311 #elif defined(CONFIG_SD_BOOT) 312 #define CFG_EXTRA_ENV_SETTINGS \ 313 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 314 "loadaddr=0x90100000\0" \ 315 "kernel_addr=0x800\0" \ 316 "ramdisk_addr=0x800000\0" \ 317 "ramdisk_size=0x2000000\0" \ 318 "fdt_high=0xa0000000\0" \ 319 "initrd_high=0xffffffffffffffff\0" \ 320 "kernel_start=0x8000\0" \ 321 "kernel_load=0xa0000000\0" \ 322 "kernel_size=0x14000\0" \ 323 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \ 324 "mmc read 0x80e00000 0x7000 0x800;" \ 325 "fsl_mc start mc 0x80a00000 0x80e00000\0" \ 326 "mcmemsize=0x70000000 \0" 327 #else 328 #define CFG_EXTRA_ENV_SETTINGS \ 329 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 330 "loadaddr=0x80100000\0" \ 331 "kernel_addr=0x100000\0" \ 332 "ramdisk_addr=0x800000\0" \ 333 "ramdisk_size=0x2000000\0" \ 334 "fdt_high=0xa0000000\0" \ 335 "initrd_high=0xffffffffffffffff\0" \ 336 "kernel_start=0x581000000\0" \ 337 "kernel_load=0xa0000000\0" \ 338 "kernel_size=0x2800000\0" \ 339 "mcmemsize=0x40000000\0" \ 340 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 341 " 0x580e00000 \0" 342 #endif /* CONFIG_TFABOOT */ 343 #endif /* CONFIG_NXP_ESBC */ 344 345 #ifdef CONFIG_TFABOOT 346 #define BOOT_TARGET_DEVICES(func) \ 347 func(USB, usb, 0) \ 348 func(MMC, mmc, 0) \ 349 func(SCSI, scsi, 0) \ 350 func(DHCP, dhcp, na) 351 #include <config_distro_bootcmd.h> 352 353 #define SD_BOOTCOMMAND \ 354 "env exists mcinitcmd && env exists secureboot "\ 355 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ 356 "&& esbc_validate $load_addr; " \ 357 "env exists mcinitcmd && run mcinitcmd " \ 358 "&& mmc read 0x80d00000 0x6800 0x800 " \ 359 "&& fsl_mc lazyapply dpl 0x80d00000; " \ 360 "run distro_bootcmd;run sd_bootcmd; " \ 361 "env exists secureboot && esbc_halt;" 362 363 #define IFC_NOR_BOOTCOMMAND \ 364 "env exists mcinitcmd && env exists secureboot "\ 365 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ 366 "&& fsl_mc lazyapply dpl 0x580d00000;" \ 367 "run distro_bootcmd;run nor_bootcmd; " \ 368 "env exists secureboot && esbc_halt;" 369 #endif 370 371 #if defined(CONFIG_FSL_MC_ENET) 372 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 373 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 374 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 375 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 376 377 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 378 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 379 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 380 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 381 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 382 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 383 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 384 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 385 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 386 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 387 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 388 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 389 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 390 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 391 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 392 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 393 394 #endif 395 396 #include <asm/fsl_secure_boot.h> 397 398 #endif /* __LS2_QDS_H */ 399