1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4  */
5 
6 #ifndef _CONFIG_DB_MV7846MP_GP_H
7 #define _CONFIG_DB_MV7846MP_GP_H
8 
9 #include <linux/sizes.h>
10 
11 /*
12  * High Level Configuration Options (easy to change)
13  */
14 
15 /*
16  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17  * for DDR ECC byte filling in the SPL before loading the main
18  * U-Boot into it.
19  */
20 
21 /* I2C */
22 #define CFG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
23 
24 /* SPI NOR flash default params, used by sf commands */
25 
26 /* Environment in SPI NOR flash */
27 
28 /*
29  * mv-common.h should be defined after CMD configs since it used them
30  * to enable certain macros
31  */
32 #include "mv-common.h"
33 
34 /*
35  * Memory layout while starting into the bin_hdr via the
36  * BootROM:
37  *
38  * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
39  * 0x4000.4030			bin_hdr start address
40  * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
41  * 0x4007.fffc			BootROM stack top
42  *
43  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
44  * L2 cache thus cannot be used.
45  */
46 
47 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
48 #define CFG_SYS_SDRAM_SIZE		SZ_1G
49 
50 #endif /* _CONFIG_DB_MV7846MP_GP_H */
51