1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * 7 * (C) Copyright 2009-2015 8 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 9 * esd electronic system design gmbh <www.esd.eu> 10 * 11 * Configuation settings for the esd MEESC board. 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 /* 18 * SoC must be defined first, before hardware.h is included. 19 * In this case SoC is defined in boards.cfg. 20 */ 21 #include <asm/hardware.h> 22 23 /* 24 * Warning: changing CONFIG_TEXT_BASE requires 25 * adapting the initial boot program. 26 * Since the linker has to swallow that define, we must use a pure 27 * hex number here! 28 */ 29 30 /* ARM asynchronous clock */ 31 #define CFG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ 32 #define CFG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ 33 34 /* Misc CPU related */ 35 36 /* 37 * Hardware drivers 38 */ 39 40 /* 41 * SDRAM: 1 bank, min 32, max 128 MB 42 * Initialized before u-boot gets started. 43 */ 44 #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ 45 #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ 46 47 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM 48 #define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE 49 50 #define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 51 #define CFG_SYS_INIT_RAM_SIZE (16 * 1024) 52 53 /* NAND flash */ 54 #ifdef CONFIG_CMD_NAND 55 # define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ 56 # define CFG_SYS_NAND_MASK_ALE (1 << 21) 57 # define CFG_SYS_NAND_MASK_CLE (1 << 22) 58 # define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 59 # define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) 60 #endif 61 62 /* hw-controller addresses */ 63 #define CFG_ET1100_BASE 0x70000000 64 65 #endif 66