1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 * Copyright 2020 NXP 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <linux/stringify.h> 14 15 #if defined(CONFIG_TARGET_P1020RDB_PC) 16 #define CFG_SLIC 17 #define __SW_BOOT_MASK 0x03 18 #define __SW_BOOT_NOR 0x5c 19 #define __SW_BOOT_SPI 0x1c 20 #define __SW_BOOT_SD 0x9c 21 #define __SW_BOOT_NAND 0xec 22 #define __SW_BOOT_PCIE 0x6c 23 #define __SW_NOR_BANK_MASK 0xfd 24 #define __SW_NOR_BANK_UP 0x00 25 #define __SW_NOR_BANK_LO 0x02 26 #define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ 27 #define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ 28 #define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ 29 #endif 30 31 /* 32 * P1020RDB-PD board has user selectable switches for evaluating different 33 * frequency and boot options for the P1020 device. The table that 34 * follow describe the available options. The front six binary number was in 35 * accordance with SW3[1:6]. 36 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 37 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 38 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 39 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 40 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 41 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 42 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 43 */ 44 #if defined(CONFIG_TARGET_P1020RDB_PD) 45 #define CFG_SLIC 46 #define __SW_BOOT_MASK 0x03 47 #define __SW_BOOT_NOR 0x64 48 #define __SW_BOOT_SPI 0x34 49 #define __SW_BOOT_SD 0x24 50 #define __SW_BOOT_NAND 0x44 51 #define __SW_BOOT_PCIE 0x74 52 #define __SW_NOR_BANK_MASK 0xfd 53 #define __SW_NOR_BANK_UP 0x00 54 #define __SW_NOR_BANK_LO 0x02 55 #define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ 56 #define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ 57 #define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ 58 /* 59 * Dynamic MTD Partition support with mtdparts 60 */ 61 #endif 62 63 #if defined(CONFIG_TARGET_P2020RDB) 64 #define __SW_BOOT_MASK 0x03 65 #define __SW_BOOT_NOR 0xc8 66 #define __SW_BOOT_SPI 0x28 67 #define __SW_BOOT_SD 0x68 68 #define __SW_BOOT_SD2 0x18 69 #define __SW_BOOT_NAND 0xe8 70 #define __SW_BOOT_PCIE 0xa8 71 #define __SW_NOR_BANK_MASK 0xfd 72 #define __SW_NOR_BANK_UP 0x00 73 #define __SW_NOR_BANK_LO 0x02 74 #define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ 75 #define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ 76 #define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ 77 /* 78 * Dynamic MTD Partition support with mtdparts 79 */ 80 #endif 81 82 #ifdef CONFIG_SDCARD 83 #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) 84 #define CFG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE 85 #define CFG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE 86 #ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR 87 #define CFG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) 88 #else 89 #define CFG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO 90 #endif 91 #elif defined(CONFIG_SPIFLASH) 92 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 93 #define CFG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE 94 #define CFG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE 95 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO 96 #elif defined(CONFIG_MTD_RAW_NAND) 97 #ifdef CONFIG_TPL_BUILD 98 #define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10) 99 #define CFG_SYS_NAND_U_BOOT_DST (0x11000000) 100 #define CFG_SYS_NAND_U_BOOT_START (0x11000000) 101 #elif defined(CONFIG_XPL_BUILD) 102 #define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10) 103 #define CFG_SYS_NAND_U_BOOT_DST 0xf8f80000 104 #define CFG_SYS_NAND_U_BOOT_START 0xf8f80000 105 #endif /* not CONFIG_TPL_BUILD */ 106 #endif 107 108 #ifndef CFG_RESET_VECTOR_ADDRESS 109 #define CFG_RESET_VECTOR_ADDRESS 0xeffffffc 110 #endif 111 112 #define CFG_SYS_CCSRBAR 0xffe00000 113 #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR 114 115 /* DDR Setup */ 116 #define SPD_EEPROM_ADDRESS 0x52 117 118 #if defined(CONFIG_TARGET_P1020RDB_PD) 119 #define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 120 #else 121 #define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 122 #endif 123 #define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19)) 124 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 125 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 126 127 /* Default settings for DDR3 */ 128 #ifndef CONFIG_TARGET_P2020RDB 129 #define CFG_SYS_DDR_CS0_BNDS 0x0000003f 130 #define CFG_SYS_DDR_CS0_CONFIG 0x80014302 131 #define CFG_SYS_DDR_CS0_CONFIG_2 0x00000000 132 #define CFG_SYS_DDR_CS1_BNDS 0x0040007f 133 #define CFG_SYS_DDR_CS1_CONFIG 0x80014302 134 #define CFG_SYS_DDR_CS1_CONFIG_2 0x00000000 135 136 #define CFG_SYS_DDR_INIT_ADDR 0x00000000 137 #define CFG_SYS_DDR_INIT_EXT_ADDR 0x00000000 138 #define CFG_SYS_DDR_MODE_CONTROL 0x00000000 139 140 #define CFG_SYS_DDR_ZQ_CONTROL 0x89080600 141 #define CFG_SYS_DDR_WRLVL_CONTROL 0x8655A608 142 #define CFG_SYS_DDR_SR_CNTR 0x00000000 143 #define CFG_SYS_DDR_RCW_1 0x00000000 144 #define CFG_SYS_DDR_RCW_2 0x00000000 145 #define CFG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 146 #define CFG_SYS_DDR_CONTROL_2 0x04401050 147 #define CFG_SYS_DDR_TIMING_4 0x00220001 148 #define CFG_SYS_DDR_TIMING_5 0x03402400 149 150 #define CFG_SYS_DDR_TIMING_3 0x00020000 151 #define CFG_SYS_DDR_TIMING_0 0x00330004 152 #define CFG_SYS_DDR_TIMING_1 0x6f6B4846 153 #define CFG_SYS_DDR_TIMING_2 0x0FA8C8CF 154 #define CFG_SYS_DDR_CLK_CTRL 0x03000000 155 #define CFG_SYS_DDR_MODE_1 0x40461520 156 #define CFG_SYS_DDR_MODE_2 0x8000c000 157 #define CFG_SYS_DDR_INTERVAL 0x0C300000 158 #endif 159 160 /* 161 * Memory map 162 * 163 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 164 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 165 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 166 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 167 * (early boot only) 168 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 169 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 170 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 171 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 172 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 173 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 174 */ 175 176 /* 177 * Local Bus Definitions 178 */ 179 #if defined(CONFIG_TARGET_P1020RDB_PD) 180 #define CFG_SYS_FLASH_BASE 0xec000000 181 #else 182 #define CFG_SYS_FLASH_BASE 0xef000000 183 #endif 184 185 #ifdef CONFIG_PHYS_64BIT 186 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) 187 #else 188 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE 189 #endif 190 191 #define CFG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \ 192 | BR_PS_16 | BR_V) 193 194 #define CFG_FLASH_OR_PRELIM 0xfc000ff7 195 196 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} 197 198 /* Nand Flash */ 199 #ifdef CONFIG_NAND_FSL_ELBC 200 #define CFG_SYS_NAND_BASE 0xff800000 201 #ifdef CONFIG_PHYS_64BIT 202 #define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull 203 #else 204 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE 205 #endif 206 207 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 208 209 #define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ 210 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 211 | BR_PS_8 /* Port Size = 8 bit */ \ 212 | BR_MS_FCM /* MSEL = FCM */ \ 213 | BR_V) /* valid */ 214 #if defined(CONFIG_TARGET_P1020RDB_PD) 215 #define CFG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 216 | OR_FCM_PGS /* Large Page*/ \ 217 | OR_FCM_CSCT \ 218 | OR_FCM_CST \ 219 | OR_FCM_CHT \ 220 | OR_FCM_SCY_1 \ 221 | OR_FCM_TRLX \ 222 | OR_FCM_EHTR) 223 #else 224 #define CFG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 225 | OR_FCM_CSCT \ 226 | OR_FCM_CST \ 227 | OR_FCM_CHT \ 228 | OR_FCM_SCY_1 \ 229 | OR_FCM_TRLX \ 230 | OR_FCM_EHTR) 231 #endif 232 #endif /* CONFIG_NAND_FSL_ELBC */ 233 234 #define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 235 #ifdef CONFIG_PHYS_64BIT 236 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 237 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR 238 /* The assembler doesn't like typecast */ 239 #define CFG_SYS_INIT_RAM_ADDR_PHYS \ 240 ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 241 CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) 242 #else 243 /* Initial L1 address */ 244 #define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR 245 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 246 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS 247 #endif 248 /* Size of used area in RAM */ 249 #define CFG_SYS_INIT_RAM_SIZE 0x00004000 250 251 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 252 253 #define CFG_SYS_CPLD_BASE 0xffa00000 254 #ifdef CONFIG_PHYS_64BIT 255 #define CFG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 256 #else 257 #define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE 258 #endif 259 /* CPLD config size: 1Mb */ 260 261 /* Vsc7385 switch */ 262 #ifdef CONFIG_VSC7385_ENET 263 #define __VSCFW_ADDR "vscfw_addr=ef000000\0" 264 #define CFG_SYS_VSC7385_BASE 0xffb00000 265 266 #ifdef CONFIG_PHYS_64BIT 267 #define CFG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 268 #else 269 #define CFG_SYS_VSC7385_BASE_PHYS CFG_SYS_VSC7385_BASE 270 #endif 271 272 /* The size of the VSC7385 firmware image */ 273 #define CFG_VSC7385_IMAGE_SIZE 8192 274 #endif 275 276 #ifndef __VSCFW_ADDR 277 #define __VSCFW_ADDR "" 278 #endif 279 280 /* 281 * Config the L2 Cache as L2 SRAM 282 */ 283 #if defined(CONFIG_XPL_BUILD) 284 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 285 #define CFG_SYS_INIT_L2_ADDR 0xf8f80000 286 #define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR 287 #define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 288 #elif defined(CONFIG_MTD_RAW_NAND) 289 #ifdef CONFIG_TPL_BUILD 290 #define CFG_SYS_INIT_L2_ADDR 0xf8f80000 291 #define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR 292 #define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 293 #else 294 #define CFG_SYS_INIT_L2_ADDR 0xf8f80000 295 #define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR 296 #define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 297 #endif /* CONFIG_TPL_BUILD */ 298 #endif 299 #endif 300 301 /* Serial Port - controlled on board with jumper J8 302 * open - index 2 303 * shorted - index 1 304 */ 305 306 #define CFG_SYS_BAUDRATE_TABLE \ 307 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 308 309 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) 310 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600) 311 312 /* I2C */ 313 #if !CONFIG_IS_ENABLED(DM_I2C) 314 #define CFG_SYS_I2C_NOPROBES { {0, 0x29} } 315 #endif 316 317 /* 318 * I2C2 EEPROM 319 */ 320 321 #define CFG_SYS_I2C_RTC_ADDR 0x68 322 #define CFG_SYS_I2C_PCA9557_ADDR 0x18 323 324 /* enable read and write access to EEPROM */ 325 326 #if defined(CONFIG_PCI) 327 /* 328 * General PCI 329 * Memory space is mapped 1-1, but I/O space must start from 0. 330 */ 331 332 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 333 #define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 334 #ifdef CONFIG_PHYS_64BIT 335 #define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 336 #else 337 #define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000 338 #endif 339 #define CFG_SYS_PCIE2_IO_VIRT 0xffc10000 340 #ifdef CONFIG_PHYS_64BIT 341 #define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 342 #else 343 #define CFG_SYS_PCIE2_IO_PHYS 0xffc10000 344 #endif 345 346 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 347 #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 348 #ifdef CONFIG_PHYS_64BIT 349 #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 350 #else 351 #define CFG_SYS_PCIE1_MEM_PHYS 0x80000000 352 #endif 353 #define CFG_SYS_PCIE1_IO_VIRT 0xffc00000 354 #ifdef CONFIG_PHYS_64BIT 355 #define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 356 #else 357 #define CFG_SYS_PCIE1_IO_PHYS 0xffc00000 358 #endif 359 #endif /* CONFIG_PCI */ 360 361 /* 362 * Environment 363 */ 364 #if defined(CONFIG_MTD_RAW_NAND) 365 #ifdef CONFIG_TPL_BUILD 366 #define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10)) 367 #endif 368 #endif 369 370 /* 371 * USB 372 */ 373 374 #ifdef CONFIG_MMC 375 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR 376 #endif 377 378 /* 379 * Miscellaneous configurable options 380 */ 381 382 /* 383 * For booting Linux, the board info and command line data 384 * have to be in the first 64 MB of memory, since this is 385 * the maximum mapped by the Linux kernel during initialization. 386 */ 387 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 388 389 /* 390 * Environment Configuration 391 */ 392 393 #include "p1_p2_bootsrc.h" 394 395 #define CFG_EXTRA_ENV_SETTINGS \ 396 "netdev=eth0\0" \ 397 "uboot=" CONFIG_UBOOTPATH "\0" \ 398 "loadaddr=1000000\0" \ 399 "bootfile=uImage\0" \ 400 "tftpflash=tftpboot $loadaddr $uboot; " \ 401 "protect off " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \ 402 "erase " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \ 403 "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) " $filesize; " \ 404 "protect on " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \ 405 "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) " $filesize\0" \ 406 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 407 "consoledev=ttyS0\0" \ 408 "ramdiskaddr=2000000\0" \ 409 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 410 "fdtaddr=1e00000\0" \ 411 "bdev=sda1\0" \ 412 "jffs2nor=mtdblock3\0" \ 413 "norbootaddr=ef080000\0" \ 414 "norfdtaddr=ef040000\0" \ 415 "jffs2nand=mtdblock9\0" \ 416 "nandbootaddr=100000\0" \ 417 "nandfdtaddr=80000\0" \ 418 "ramdisk_size=120000\0" \ 419 __VSCFW_ADDR \ 420 MAP_NOR_LO_CMD(map_lowernorbank) \ 421 MAP_NOR_UP_CMD(map_uppernorbank) \ 422 RST_NOR_CMD(norboot) \ 423 RST_NOR_LO_CMD(norlowerboot) \ 424 RST_NOR_UP_CMD(norupperboot) \ 425 RST_SPI_CMD(spiboot) \ 426 RST_SD_CMD(sdboot) \ 427 RST_SD2_CMD(sd2boot) \ 428 RST_NAND_CMD(nandboot) \ 429 RST_PCIE_CMD(pciboot) \ 430 RST_DEF_CMD(defboot) \ 431 "" 432 433 #endif /* __CONFIG_H */ 434