1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2020 Hitachi Power Grids. All rights reserved. 4 */ 5 6 #ifndef __CONFIG_PG_WCOM_SELI8_H 7 #define __CONFIG_PG_WCOM_SELI8_H 8 9 /* PAXK FPGA Definitions */ 10 #define CFG_SYS_CSPR3_EXT (0x00) 11 #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ 12 CSPR_PORT_SIZE_8 | \ 13 CSPR_MSEL_GPCM | \ 14 CSPR_V) 15 #define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) 16 #define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ 17 CSOR_GPCM_TRHZ_40) 18 #define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ 19 FTIM0_GPCM_TEADC(0x7) | \ 20 FTIM0_GPCM_TEAHC(0x2)) 21 #define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ 22 FTIM1_GPCM_TRAD(0x12)) 23 #define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ 24 FTIM2_GPCM_TCH(0x1) | \ 25 FTIM2_GPCM_TWP(0x12)) 26 #define CFG_SYS_CS3_FTIM3 0x04000000 27 28 /* PRST */ 29 #define KM_LIU_RST 0 30 #define KM_PAXK_RST 1 31 #define KM_DBG_ETH_RST 15 32 33 /* QRIO GPIOs used for deblocking */ 34 #define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A 35 #define KM_I2C_DEBLOCK_SCL 20 36 #define KM_I2C_DEBLOCK_SDA 21 37 38 #include "km/pg-wcom-ls102xa.h" 39 40 #endif /* __CONFIG_PG_WCOM_SELI8_H */ 41