1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * Ilko Iliev <www.ronetix.at> 7 * 8 * Configuration settings for the RONETIX PM9263 board. 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 #include <asm/hardware.h> 19 20 /* ARM asynchronous clock */ 21 22 #define MASTER_PLL_DIV 6 23 #define MASTER_PLL_MUL 65 24 #define MAIN_PLL_DIV 2 /* 2 or 4 */ 25 #define CFG_SYS_AT91_MAIN_CLOCK 18432000 26 #define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 27 28 /* clocks */ 29 #define CFG_SYS_MOR_VAL \ 30 (AT91_PMC_MOR_MOSCEN | \ 31 (255 << 8)) /* Main Oscillator Start-up Time */ 32 #define CFG_SYS_PLLAR_VAL \ 33 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ 34 AT91_PMC_PLLXR_OUT(3) | \ 35 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ 36 (2 << 28) | /* PLL Clock Frequency Range */ \ 37 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 38 39 #if (MAIN_PLL_DIV == 2) 40 /* PCK/2 = MCK Master Clock from PLLA */ 41 #define CFG_SYS_MCKR1_VAL \ 42 (AT91_PMC_MCKR_CSS_SLOW | \ 43 AT91_PMC_MCKR_PRES_1 | \ 44 AT91_PMC_MCKR_MDIV_2) 45 /* PCK/2 = MCK Master Clock from PLLA */ 46 #define CFG_SYS_MCKR2_VAL \ 47 (AT91_PMC_MCKR_CSS_PLLA | \ 48 AT91_PMC_MCKR_PRES_1 | \ 49 AT91_PMC_MCKR_MDIV_2) 50 #else 51 /* PCK/4 = MCK Master Clock from PLLA */ 52 #define CFG_SYS_MCKR1_VAL \ 53 (AT91_PMC_MCKR_CSS_SLOW | \ 54 AT91_PMC_MCKR_PRES_1 | \ 55 AT91_PMC_MCKR_MDIV_4) 56 /* PCK/4 = MCK Master Clock from PLLA */ 57 #define CFG_SYS_MCKR2_VAL \ 58 (AT91_PMC_MCKR_CSS_PLLA | \ 59 AT91_PMC_MCKR_PRES_1 | \ 60 AT91_PMC_MCKR_MDIV_4) 61 #endif 62 /* define PDC[31:16] as DATA[31:16] */ 63 #define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000 64 /* no pull-up for D[31:16] */ 65 #define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 66 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 67 #define CFG_SYS_MATRIX_EBI0CSA_VAL \ 68 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 69 AT91_MATRIX_CSA_EBI_CS1A) 70 71 /* SDRAM */ 72 /* SDRAMC_MR Mode register */ 73 #define CFG_SYS_SDRC_MR_VAL1 0 74 /* SDRAMC_TR - Refresh Timer register */ 75 #define CFG_SYS_SDRC_TR_VAL1 0x3AA 76 /* SDRAMC_CR - Configuration register*/ 77 #define CFG_SYS_SDRC_CR_VAL \ 78 (AT91_SDRAMC_NC_9 | \ 79 AT91_SDRAMC_NR_13 | \ 80 AT91_SDRAMC_NB_4 | \ 81 AT91_SDRAMC_CAS_2 | \ 82 AT91_SDRAMC_DBW_32 | \ 83 (2 << 8) | /* tWR - Write Recovery Delay */ \ 84 (7 << 12) | /* tRC - Row Cycle Delay */ \ 85 (2 << 16) | /* tRP - Row Precharge Delay */ \ 86 (2 << 20) | /* tRCD - Row to Column Delay */ \ 87 (5 << 24) | /* tRAS - Active to Precharge Delay */ \ 88 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ 89 90 /* Memory Device Register -> SDRAM */ 91 #define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 92 #define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 93 #define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 94 #define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 95 #define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 96 #define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 97 #define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 98 #define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 99 #define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 100 #define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 101 #define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 102 #define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 103 #define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 104 #define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 105 #define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 106 #define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 107 #define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 108 #define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 109 110 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 111 #define CFG_SYS_SMC0_SETUP0_VAL \ 112 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 113 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 114 #define CFG_SYS_SMC0_PULSE0_VAL \ 115 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 116 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 117 #define CFG_SYS_SMC0_CYCLE0_VAL \ 118 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 119 #define CFG_SYS_SMC0_MODE0_VAL \ 120 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 121 AT91_SMC_MODE_DBW_16 | \ 122 AT91_SMC_MODE_TDF | \ 123 AT91_SMC_MODE_TDF_CYCLE(6)) 124 125 /* user reset enable */ 126 #define CFG_SYS_RSTC_RMR_VAL \ 127 (AT91_RSTC_KEY | \ 128 AT91_RSTC_CR_PROCRST | \ 129 AT91_RSTC_MR_ERSTL(1) | \ 130 AT91_RSTC_MR_ERSTL(2)) 131 132 /* Disable Watchdog */ 133 #define CFG_SYS_WDTC_WDMR_VAL \ 134 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 135 AT91_WDT_MR_WDV(0xfff) | \ 136 AT91_WDT_MR_WDDIS | \ 137 AT91_WDT_MR_WDD(0xfff)) 138 139 /* SDRAM */ 140 #define PHYS_SDRAM 0x20000000 141 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 142 143 /* NOR flash, if populated */ 144 #define PHYS_FLASH_1 0x10000000 145 #define CFG_SYS_FLASH_BASE PHYS_FLASH_1 146 147 /* NAND flash */ 148 #ifdef CONFIG_CMD_NAND 149 #define CFG_SYS_NAND_BASE 0x40000000 150 /* our ALE is AD21 */ 151 #define CFG_SYS_NAND_MASK_ALE (1 << 21) 152 /* our CLE is AD22 */ 153 #define CFG_SYS_NAND_MASK_CLE (1 << 22) 154 #define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 155 #define CFG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) 156 157 #endif 158 159 /* PSRAM */ 160 #define PHYS_PSRAM 0x70000000 161 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ 162 163 /* USB */ 164 #define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 165 166 #define CFG_EXTRA_ENV_SETTINGS \ 167 "partition=nand0,0\0" \ 168 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 169 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 170 "fbcon=rotate:3 " \ 171 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 172 "addip=setenv bootargs $(bootargs) " \ 173 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 174 ":$(hostname):eth0:off\0" \ 175 "ramboot=tftpboot 0x22000000 vmImage;" \ 176 "run ramargs;run addip;bootm 22000000\0" \ 177 "nfsboot=tftpboot 0x22000000 vmImage;" \ 178 "run nfsargs;run addip;bootm 22000000\0" \ 179 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 180 "" 181 182 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM 183 184 #endif 185