1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4  */
5 
6 #ifndef __CONFIG_RK3308_COMMON_H
7 #define __CONFIG_RK3308_COMMON_H
8 
9 #include "rockchip-common.h"
10 
11 #define CFG_IRAM_BASE			0xfff80000
12 
13 #define CFG_SYS_SDRAM_BASE		0
14 #define SDRAM_MAX_SIZE			0xff000000
15 
16 #define ENV_MEM_LAYOUT_SETTINGS		\
17 	"scriptaddr=0x00500000\0"	\
18 	"script_offset_f=0xffe000\0"	\
19 	"script_size_f=0x2000\0"	\
20 	"pxefile_addr_r=0x00600000\0"	\
21 	"fdt_addr_r=0x01e00000\0"	\
22 	"fdtoverlay_addr_r=0x01f00000\0"	\
23 	"kernel_addr_r=0x02080000\0"	\
24 	"ramdisk_addr_r=0x06000000\0"	\
25 	"kernel_comp_addr_r=0x08000000\0"	\
26 	"kernel_comp_size=0x2000000\0"
27 
28 #define CFG_EXTRA_ENV_SETTINGS		\
29 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"	\
30 	"partitions=" PARTS_DEFAULT	\
31 	ENV_MEM_LAYOUT_SETTINGS		\
32 	ROCKCHIP_DEVICE_SETTINGS	\
33 	"boot_targets=" BOOT_TARGETS "\0"
34 
35 #endif /* __CONFIG_RK3308_COMMON_H */
36