1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef __CONFIG_RK3399_COMMON_H 7 #define __CONFIG_RK3399_COMMON_H 8 9 #include "rockchip-common.h" 10 11 #define CFG_IRAM_BASE 0xff8c0000 12 13 #define CFG_SYS_SDRAM_BASE 0 14 #define SDRAM_MAX_SIZE 0xf8000000 15 16 #ifndef CONFIG_XPL_BUILD 17 18 #ifndef ROCKCHIP_DEVICE_SETTINGS 19 #define ROCKCHIP_DEVICE_SETTINGS 20 #endif 21 22 #define ENV_MEM_LAYOUT_SETTINGS \ 23 "scriptaddr=0x00c00000\0" \ 24 "script_offset_f=0xffe000\0" \ 25 "script_size_f=0x2000\0" \ 26 "pxefile_addr_r=0x00e00000\0" \ 27 "kernel_addr_r=0x02000000\0" \ 28 "kernel_comp_addr_r=0x0a000000\0" \ 29 "fdt_addr_r=0x12000000\0" \ 30 "fdtoverlay_addr_r=0x12100000\0" \ 31 "ramdisk_addr_r=0x12180000\0" \ 32 "kernel_comp_size=0x8000000\0" 33 34 #define CFG_EXTRA_ENV_SETTINGS \ 35 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 36 "partitions=" PARTS_DEFAULT \ 37 ENV_MEM_LAYOUT_SETTINGS \ 38 ROCKCHIP_DEVICE_SETTINGS \ 39 "boot_targets=" BOOT_TARGETS "\0" 40 41 #endif /* CONFIG_XPL_BUILD */ 42 43 #endif /* __CONFIG_RK3399_COMMON_H */ 44