1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2024 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef __CONFIG_RK3576_COMMON_H 7 #define __CONFIG_RK3576_COMMON_H 8 9 #define CFG_CPUID_OFFSET 0xa 10 11 #include "rockchip-common.h" 12 13 #define CFG_IRAM_BASE 0x3ff80000 14 15 #define CFG_SYS_SDRAM_BASE 0x40000000 16 /* Used by board_get_usable_ram_top(), space below the 4G address boundary */ 17 #define SDRAM_MAX_SIZE (SZ_4G - CFG_SYS_SDRAM_BASE) 18 19 #ifndef ROCKCHIP_DEVICE_SETTINGS 20 #define ROCKCHIP_DEVICE_SETTINGS 21 #endif 22 23 #define ENV_MEM_LAYOUT_SETTINGS \ 24 "scriptaddr=0x40c00000\0" \ 25 "script_offset_f=0xffe000\0" \ 26 "script_size_f=0x2000\0" \ 27 "pxefile_addr_r=0x40e00000\0" \ 28 "kernel_addr_r=0x42000000\0" \ 29 "kernel_comp_addr_r=0x4a000000\0" \ 30 "fdt_addr_r=0x52000000\0" \ 31 "fdtoverlay_addr_r=0x52100000\0" \ 32 "ramdisk_addr_r=0x52180000\0" \ 33 "kernel_comp_size=0x8000000\0" 34 35 #define CFG_EXTRA_ENV_SETTINGS \ 36 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 37 ENV_MEM_LAYOUT_SETTINGS \ 38 ROCKCHIP_DEVICE_SETTINGS \ 39 "boot_targets=" BOOT_TARGETS "\0" 40 41 #endif /* __CONFIG_RK3576_COMMON_H */ 42