1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd 4 * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. 5 */ 6 7 #ifndef __CONFIG_RK3588_COMMON_H 8 #define __CONFIG_RK3588_COMMON_H 9 10 #include "rockchip-common.h" 11 12 #define CFG_IRAM_BASE 0xff000000 13 14 #define CFG_SYS_SDRAM_BASE 0 15 #define SDRAM_MAX_SIZE 0xf0000000 16 17 #ifndef ROCKCHIP_DEVICE_SETTINGS 18 #define ROCKCHIP_DEVICE_SETTINGS 19 #endif 20 21 #define ENV_MEM_LAYOUT_SETTINGS \ 22 "scriptaddr=0x00c00000\0" \ 23 "script_offset_f=0xffe000\0" \ 24 "script_size_f=0x2000\0" \ 25 "pxefile_addr_r=0x00e00000\0" \ 26 "kernel_addr_r=0x02000000\0" \ 27 "kernel_comp_addr_r=0x0a000000\0" \ 28 "fdt_addr_r=0x12000000\0" \ 29 "fdtoverlay_addr_r=0x12100000\0" \ 30 "ramdisk_addr_r=0x12180000\0" \ 31 "kernel_comp_size=0x8000000\0" 32 33 #define CFG_EXTRA_ENV_SETTINGS \ 34 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 35 ENV_MEM_LAYOUT_SETTINGS \ 36 ROCKCHIP_DEVICE_SETTINGS \ 37 "boot_targets=" BOOT_TARGETS "\0" 38 39 #endif /* __CONFIG_RK3588_COMMON_H */ 40