1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. 5 */ 6 7 #ifndef __CONFIG_RV1126_COMMON_H 8 #define __CONFIG_RV1126_COMMON_H 9 10 #include "rockchip-common.h" 11 12 #define CFG_SYS_HZ_CLOCK 24000000 13 14 #define CFG_IRAM_BASE 0xff700000 15 16 #define GICD_BASE 0xfeff1000 17 #define GICC_BASE 0xfeff2000 18 19 #define CFG_SYS_SDRAM_BASE 0 20 #define SDRAM_MAX_SIZE 0xfd000000 21 22 /* memory size > 128MB */ 23 #define ENV_MEM_LAYOUT_SETTINGS \ 24 "scriptaddr=0x00000000\0" \ 25 "pxefile_addr_r=0x00100000\0" \ 26 "fdt_addr_r=0x08300000\0" \ 27 "fdtoverlay_addr_r=0x02000000\0" \ 28 "kernel_addr_r=0x02008000\0" \ 29 "ramdisk_addr_r=0x0a400000\0" 30 31 #define CFG_EXTRA_ENV_SETTINGS \ 32 "fdt_high=0x0fffffff\0" \ 33 "initrd_high=0x0fffffff\0" \ 34 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 35 "partitions=" PARTS_DEFAULT \ 36 ENV_MEM_LAYOUT_SETTINGS \ 37 ROCKCHIP_DEVICE_SETTINGS \ 38 "boot_targets=" BOOT_TARGETS "\0" 39 40 #endif /* __CONFIG_RV1126_COMMON_H */ 41