1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the SAMA5D3xEK board. 4 * 5 * Copyright (C) 2012 - 2013 Atmel 6 * 7 * based on at91sam9m10g45ek.h by: 8 * Stelian Pop <stelian@popies.net> 9 * Lead Tech Design <www.leadtechdesign.com> 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #include "at91-sama5_common.h" 16 17 /* 18 * This needs to be defined for the OHCI code to work but it is defined as 19 * ATMEL_ID_UHPHS in the CPU specific header files. 20 */ 21 #define ATMEL_ID_UHP 32 22 23 /* 24 * Specify the clock enable bit in the PMC_SCER register. 25 */ 26 #define ATMEL_PMC_UHP (1 << 6) 27 28 /* NOR flash */ 29 #ifdef CONFIG_MTD_NOR_FLASH 30 #define CFG_SYS_FLASH_BASE 0x10000000 31 #endif 32 33 /* SDRAM */ 34 #define CFG_SYS_SDRAM_BASE 0x20000000 35 #define CFG_SYS_SDRAM_SIZE 0x20000000 36 37 /* SerialFlash */ 38 39 /* NAND flash */ 40 #ifdef CONFIG_CMD_NAND 41 #define CFG_SYS_NAND_BASE 0x60000000 42 /* our ALE is AD21 */ 43 #define CFG_SYS_NAND_MASK_ALE (1 << 21) 44 /* our CLE is AD22 */ 45 #define CFG_SYS_NAND_MASK_CLE (1 << 22) 46 #endif 47 48 /* SPL */ 49 50 #endif 51