1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2017-2024 Intel Corporation <www.intel.com> 4 * Copyright (C) 2025 Altera Corporation <www.altera.com> 5 * 6 */ 7 8 #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__ 9 #define __CONFIG_SOCFPGA_SOC64_COMMON_H__ 10 11 #include <asm/arch/base_addr_soc64.h> 12 #include <asm/arch/handoff_soc64.h> 13 #include <linux/stringify.h> 14 15 /* 16 * U-Boot general configurations 17 */ 18 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ 19 #define CPU_RELEASE_ADDR 0xFFD12210 20 21 /* 22 * Share sysmgr.boot_scratch_cold6 & 7 (64bit) with VBAR_LE3_BASE_ADDR 23 * Indicate L2 reset is done. HPS should trigger warm reset via RMR_EL3. 24 */ 25 #define L2_RESET_DONE_REG 0xFFD12218 26 27 /* sysmgr.boot_scratch_cold8 bit 17 (1bit) will be used to check whether CPU0 28 * is being powered off/on from kernel 29 */ 30 #define BOOT_SCRATCH_COLD8 0xFFD12220 31 32 /* Magic word to indicate L2 reset is completed */ 33 #define L2_RESET_DONE_STATUS 0x1228E5E7 34 35 /* 36 * U-Boot console configurations 37 */ 38 39 /* Extend size of kernel image for uncompression */ 40 41 /* 42 * U-Boot run time memory configurations 43 */ 44 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) 45 #define CFG_SYS_INIT_RAM_ADDR 0x0 46 #define CFG_SYS_INIT_RAM_SIZE 0x80000 47 #else 48 #define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 49 #define CFG_SYS_INIT_RAM_SIZE 0x40000 50 #endif 51 52 /* 53 * U-Boot environment configurations 54 */ 55 56 #define CFG_SYS_NAND_U_BOOT_SIZE (1 * 1024 * 1024) 57 #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE 58 59 /* 60 * Environment variable 61 */ 62 #if IS_ENABLED(CONFIG_DISTRO_DEFAULTS) 63 #if IS_ENABLED(CONFIG_CMD_MMC) 64 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 65 #else 66 #define BOOT_TARGET_DEVICES_MMC(func) 67 #endif 68 69 #if IS_ENABLED(CONFIG_CMD_SF) 70 #define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) 71 #else 72 #define BOOT_TARGET_DEVICES_QSPI(func) 73 #endif 74 75 #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ 76 "bootcmd_qspi=ubi detach; sf probe && " \ 77 "setenv mtdids 'nor0=nor0,nand0=nand.0' && " \ 78 "setenv mtdparts 'mtdparts=nor0:66m(u-boot),190m(root); " \ 79 "nand.0:2m(nand_uboot),500m(nand_root)' && " \ 80 "env select UBI; saveenv && " \ 81 "ubi part root && " \ 82 "if ubi part root && ubi readvol ${scriptaddr} script; " \ 83 "then echo QSPI: Running script from UBIFS; " \ 84 "elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; " \ 85 "then echo QSPI: Running script from JFFS2; fi; " \ 86 "echo QSPI: Trying to boot script at ${scriptaddr} && " \ 87 "source ${scriptaddr}; " \ 88 "echo QSPI: SCRIPT FAILED: continuing...; ubi detach;\0" 89 90 #define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ 91 "qspi " 92 93 #if IS_ENABLED(CONFIG_CMD_NAND) 94 #define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand, na) 95 #else 96 #define BOOT_TARGET_DEVICES_NAND(func) 97 #endif 98 99 #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ 100 "bootcmd_nand=ubi detach && " \ 101 "setenv mtdids 'nor0=nor0,nand0=nand.0' && " \ 102 "setenv mtdparts 'mtdparts=nor0:66m(qspi_uboot),190m(qspi_root);" \ 103 "nand.0:2m(u-boot),500m(root)' && " \ 104 "env select UBI; saveenv && " \ 105 "ubi part root && " \ 106 "ubi readvol ${scriptaddr} script && " \ 107 "echo NAND: Trying to boot script at ${scriptaddr} && " \ 108 "source ${scriptaddr}; " \ 109 "echo NAND: SCRIPT FAILED: continuing...; ubi detach;\0" 110 111 #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ 112 "nand " 113 114 #define BOOT_TARGET_DEVICES(func) \ 115 BOOT_TARGET_DEVICES_MMC(func) \ 116 BOOT_TARGET_DEVICES_QSPI(func) \ 117 BOOT_TARGET_DEVICES_NAND(func) 118 119 #include <config_distro_bootcmd.h> 120 121 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) 122 123 #define CFG_EXTRA_ENV_SETTINGS \ 124 "kernel_addr_r=0x82000000\0" \ 125 "fdt_addr_r=0x86000000\0" \ 126 "qspiscriptaddr=0x02110000\0" \ 127 "scriptsize=0x00010000\0" \ 128 "qspibootimageaddr=0x02120000\0" \ 129 "bootimagesize=0x03200000\0" \ 130 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 131 "bootfile=" CONFIG_BOOTFILE "\0" \ 132 "mmcroot=/dev/mmcblk0p2\0" \ 133 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 134 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 135 "linux_qspi_enable=if sf probe; then " \ 136 "echo Enabling QSPI at Linux DTB...;" \ 137 "fdt addr ${fdt_addr}; fdt resize;" \ 138 "fdt set /soc/spi@108d2000 status okay;" \ 139 "if fdt set /clocks/qspi-clk clock-frequency" \ 140 " ${qspi_clock}; then echo QSPI clock frequency updated;" \ 141 " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ 142 " ${qspi_clock}; then echo QSPI clock frequency updated;" \ 143 " else fdt set /clocks/qspi-clk clock-frequency" \ 144 " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ 145 "scriptaddr=0x81000000\0" \ 146 "scriptfile=boot.scr\0" \ 147 "socfpga_legacy_reset_compat=1\0" \ 148 "smc_fid_rd=0xC2000007\0" \ 149 "smc_fid_wr=0xC2000008\0" \ 150 "smc_fid_upd=0xC2000009\0 " \ 151 BOOTENV 152 153 #else 154 155 #define CFG_EXTRA_ENV_SETTINGS \ 156 "kernel_addr_r=0x2000000\0" \ 157 "fdt_addr_r=0x6000000\0" \ 158 "qspiscriptaddr=0x02110000\0" \ 159 "scriptsize=0x00010000\0" \ 160 "qspibootimageaddr=0x02120000\0" \ 161 "bootimagesize=0x03200000\0" \ 162 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 163 "bootfile=" CONFIG_BOOTFILE "\0" \ 164 "mmcroot=/dev/mmcblk0p2\0" \ 165 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 166 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 167 "linux_qspi_enable=if sf probe; then " \ 168 "echo Enabling QSPI at Linux DTB...;" \ 169 "fdt addr ${fdt_addr}; fdt resize;" \ 170 "fdt set /soc/spi@ff8d2000 status okay;" \ 171 "if fdt set /soc/clocks/qspi-clk clock-frequency" \ 172 " ${qspi_clock}; then echo QSPI clock frequency updated;" \ 173 " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ 174 " ${qspi_clock}; then echo QSPI clock frequency updated;" \ 175 " else fdt set /clocks/qspi-clk clock-frequency" \ 176 " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ 177 "scriptaddr=0x05FF0000\0" \ 178 "scriptfile=boot.scr\0" \ 179 "nandroot=ubi0:rootfs\0" \ 180 "socfpga_legacy_reset_compat=1\0" \ 181 "smc_fid_rd=0xC2000007\0" \ 182 "smc_fid_wr=0xC2000008\0" \ 183 "smc_fid_upd=0xC2000009\0 " \ 184 BOOTENV 185 #endif /*#IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)*/ 186 187 #else 188 189 #define CFG_EXTRA_ENV_SETTINGS \ 190 "kernel_comp_addr_r=0x9000000\0" \ 191 "kernel_comp_size=0x01000000\0" \ 192 "qspibootimageaddr=0x020E0000\0" \ 193 "qspifdtaddr=0x020D0000\0" \ 194 "bootimagesize=0x01F00000\0" \ 195 "fdtimagesize=0x00010000\0" \ 196 "qspiload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \ 197 "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize}\0" \ 198 "qspiboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ 199 "rootfstype=jffs2 rootwait;booti ${loadaddr} - ${fdt_addr}\0" \ 200 "qspifitload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize}\0" \ 201 "qspifitboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ 202 "rootfstype=jffs2 rootwait;bootm ${loadaddr}\0" \ 203 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 204 "bootfile=" CONFIG_BOOTFILE "\0" \ 205 "fdt_addr=8000000\0" \ 206 "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ 207 "mmcroot=/dev/mmcblk0p2\0" \ 208 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ 209 " root=${mmcroot} rw rootwait;" \ 210 "booti ${loadaddr} - ${fdt_addr}\0" \ 211 "mmcload=mmc rescan;" \ 212 "load mmc 0:1 ${loadaddr} ${bootfile};" \ 213 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ 214 "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \ 215 " root=${mmcroot} rw rootwait;" \ 216 "bootm ${loadaddr}\0" \ 217 "mmcfitload=mmc rescan;" \ 218 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \ 219 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 220 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 221 "linux_qspi_enable=if sf probe; then " \ 222 "echo Enabling QSPI at Linux DTB...;" \ 223 "fdt addr ${fdt_addr}; fdt resize;" \ 224 "fdt set /soc/spi@ff8d2000 status okay;" \ 225 "if fdt set /soc/clocks/qspi-clk clock-frequency" \ 226 " ${qspi_clock}; then echo QSPI clock frequency updated;" \ 227 " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ 228 " ${qspi_clock}; then echo QSPI clock frequency updated;" \ 229 " else fdt set /clocks/qspi-clk clock-frequency" \ 230 " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ 231 "scriptaddr=0x02100000\0" \ 232 "scriptfile=u-boot.scr\0" \ 233 "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ 234 "then source ${scriptaddr}:script; fi\0" \ 235 "nandfitboot=setenv bootargs " CONFIG_BOOTARGS \ 236 " root=${nandroot} rw rootwait rootfstype=ubifs ubi.mtd=1; " \ 237 "bootm ${loadaddr}\0" \ 238 "nandfitload=ubi part root; ubi readvol ${loadaddr} kernel\0" \ 239 "socfpga_legacy_reset_compat=1\0" \ 240 "smc_fid_rd=0xC2000007\0" \ 241 "smc_fid_wr=0xC2000008\0" \ 242 "smc_fid_upd=0xC2000009\0 " 243 #endif /*#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS)*/ 244 245 /* 246 * External memory configurations 247 */ 248 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) 249 #define PHYS_SDRAM_1 0x80000000 250 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) 251 #define CFG_SYS_SDRAM_BASE 0x80000000 252 #else 253 #define PHYS_SDRAM_1 0x0 254 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) 255 #define CFG_SYS_SDRAM_BASE 0 256 #endif 257 258 /* 259 * Serial / UART configurations 260 */ 261 #define CFG_SYS_NS16550_CLK 100000000 262 263 /* 264 * SDMMC configurations 265 */ 266 /* 267 * Flash configurations 268 */ 269 270 /* 271 * L4 Watchdog 272 */ 273 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 274 #ifndef __ASSEMBLY__ 275 unsigned int cm_get_l4_sys_free_clk_hz(void); 276 #define CFG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) 277 #endif 278 #else 279 #define CFG_DW_WDT_CLOCK_KHZ 100000 280 #endif 281 282 /* 283 * SPL memory layout 284 * 285 * On chip RAM 286 * 0xFFE0_0000 ...... Start of OCRAM 287 * SPL code, rwdata 288 * empty space 289 * 0xFFEx_xxxx ...... Top of stack (grows down) 290 * 0xFFEy_yyyy ...... Global Data 291 * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN) 292 * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB) 293 * 0xFFE3_FFFF ...... End of OCRAM 294 * 295 * SDRAM 296 * 0x0000_0000 ...... Start of SDRAM_1 297 * unused / empty space for image loading 298 * Size 64MB ...... MALLOC (size CONFIG_SPL_SYS_MALLOC_SIZE) 299 * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE) 300 * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) 301 * 302 */ 303 304 #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */ 305