1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * ti_omap3_common.h 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 6 * 7 * For more details, please see the technical documents listed at 8 * https://www.ti.com/product/omap3530 9 * https://www.ti.com/product/omap3630 10 * https://www.ti.com/product/dm3730 11 */ 12 13 #ifndef __CONFIG_TI_OMAP3_COMMON_H__ 14 #define __CONFIG_TI_OMAP3_COMMON_H__ 15 16 /* 17 * High Level Configuration Options 18 */ 19 20 #include <asm/arch/cpu.h> 21 #include <asm/arch/omap.h> 22 23 /* Clock Defines */ 24 #define V_OSCK 26000000 /* Clock output from T2 */ 25 #define V_SCLK (V_OSCK >> 1) 26 27 /* NS16550 Configuration */ 28 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 29 #define CFG_SYS_NS16550_CLK V_NS16550_CLK 30 #define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 31 115200} 32 33 /* Select serial console configuration */ 34 #ifdef CONFIG_XPL_BUILD 35 #define CFG_SYS_NS16550_COM1 OMAP34XX_UART1 36 #define CFG_SYS_NS16550_COM2 OMAP34XX_UART2 37 #define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 38 #endif 39 40 /* Physical Memory Map */ 41 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 42 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 43 44 /* 45 * OMAP3 has 12 GP timers, they can be driven by the system clock 46 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 47 * This rate is divided by a local divisor. 48 */ 49 #define CFG_SYS_TIMERBASE (OMAP34XX_GPT2) 50 51 /* SPL */ 52 53 #ifdef CONFIG_MTD_RAW_NAND 54 #define CFG_SYS_NAND_BASE 0x30000000 55 #endif 56 57 /* Now bring in the rest of the common code. */ 58 #include <configs/ti_armv7_omap.h> 59 60 #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ 61