1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Samsung Electronics 4 * Heungjun Kim <riverful.kim@samsung.com> 5 * 6 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board. 7 */ 8 9 #ifndef __CONFIG_TRATS_H 10 #define __CONFIG_TRATS_H 11 12 #include <configs/exynos4-common.h> 13 14 #ifndef CONFIG_SYS_L2CACHE_OFF 15 #define CFG_SYS_PL310_BASE 0x10502000 16 #endif 17 18 /* TRATS has 4 banks of DRAM */ 19 #define CFG_SYS_SDRAM_BASE 0x40000000 20 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE 21 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ 22 23 /* Tizen - partitions definitions */ 24 #define PARTS_CSA "csa-mmc" 25 #define PARTS_BOOT "boot" 26 #define PARTS_QBOOT "qboot" 27 #define PARTS_CSC "csc" 28 #define PARTS_ROOT "platform" 29 #define PARTS_DATA "data" 30 #define PARTS_UMS "ums" 31 32 #define PARTS_DEFAULT \ 33 "uuid_disk=${uuid_gpt_disk};" \ 34 "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ 35 "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ 36 "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ 37 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ 38 "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ 39 "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ 40 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ 41 42 #define CFG_DFU_ALT \ 43 "u-boot raw 0x80 0x400;" \ 44 "/uImage ext4 0 2;" \ 45 "/modem.bin ext4 0 2;" \ 46 "/exynos4210-trats.dtb ext4 0 2;" \ 47 ""PARTS_CSA" part 0 1;" \ 48 ""PARTS_BOOT" part 0 2;" \ 49 ""PARTS_QBOOT" part 0 3;" \ 50 ""PARTS_CSC" part 0 4;" \ 51 ""PARTS_ROOT" part 0 5;" \ 52 ""PARTS_DATA" part 0 6;" \ 53 ""PARTS_UMS" part 0 7;" \ 54 "params.bin raw 0x38 0x8;" \ 55 "/Image.itb ext4 0 2\0" 56 57 #define CFG_EXTRA_ENV_SETTINGS \ 58 "bootk=" \ 59 "run loaduimage;" \ 60 "if run loaddtb; then " \ 61 "bootm 0x40007FC0 - ${fdtaddr};" \ 62 "fi;" \ 63 "bootm 0x40007FC0;\0" \ 64 "updatebackup=" \ 65 "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ 66 "mmc dev 0 0\0" \ 67 "updatebootb=" \ 68 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ 69 "lpj=lpj=3981312\0" \ 70 "nfsboot=" \ 71 "setenv bootargs root=/dev/nfs rw " \ 72 "nfsroot=${nfsroot},nolock,tcp " \ 73 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 74 "${netmask}:generic:usb0:off ${console} ${meminfo}" \ 75 "; run bootk\0" \ 76 "ramfsboot=" \ 77 "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \ 78 "${console} ${meminfo} " \ 79 "initrd=0x43000000,8M ramdisk=8192\0" \ 80 "mmcboot=" \ 81 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 82 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ 83 "run bootk\0" \ 84 "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ 85 "boottrace=setenv opts initcall_debug; run bootcmd\0" \ 86 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ 87 "verify=n\0" \ 88 "rootfstype=ext4\0" \ 89 "console=console=ttySAC2,115200n8\0" \ 90 "meminfo=crashkernel=32M@0x50000000\0" \ 91 "nfsroot=/nfsroot/arm\0" \ 92 "bootblock=10\0" \ 93 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ 94 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ 95 "${fdtfile}\0" \ 96 "mmcdev=0\0" \ 97 "mmcbootpart=2\0" \ 98 "mmcrootpart=5\0" \ 99 "opts=always_resume=1\0" \ 100 "partitions=" PARTS_DEFAULT \ 101 "dfu_alt_info=" CFG_DFU_ALT \ 102 "spladdr=0x40000100\0" \ 103 "splsize=0x200\0" \ 104 "splfile=falcon.bin\0" \ 105 "spl_export=" \ 106 "setexpr spl_imgsize ${splsize} + 8 ;" \ 107 "setenv spl_imgsize 0x${spl_imgsize};" \ 108 "setexpr spl_imgaddr ${spladdr} - 8 ;" \ 109 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ 110 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ 111 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 112 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ 113 "spl export atags 0x40007FC0;" \ 114 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ 115 "mw.l ${spl_addr_tmp} ${splsize};" \ 116 "ext4write mmc ${mmcdev}:${mmcbootpart}" \ 117 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ 118 "setenv spl_imgsize;" \ 119 "setenv spl_imgaddr;" \ 120 "setenv spl_addr_tmp;\0" \ 121 ENV_ITB \ 122 "fdtaddr=40800000\0" \ 123 124 /* Falcon mode definitions */ 125 126 /* GPT */ 127 128 /* Download menu - definitions for check keys */ 129 #ifndef __ASSEMBLY__ 130 131 #define KEY_PWR_PMIC_NAME "MAX8997_PMIC" 132 #define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 133 #define KEY_PWR_STATUS_MASK (1 << 0) 134 #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 135 #define KEY_PWR_INTERRUPT_MASK (1 << 0) 136 137 #define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 138 #define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 139 #endif /* __ASSEMBLY__ */ 140 141 #endif /* __CONFIG_H */ 142