1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2024-2025 Renesas Electronics Corp. 4 */ 5 6 #ifndef __INCLUDE_DBSC5_H__ 7 #define __INCLUDE_DBSC5_H__ 8 9 /* The number of channels V4H has */ 10 #define DRAM_CH_CNT 4 11 /* The number of slices V4H has */ 12 #define SLICE_CNT 2 13 /* The number of chip select V4H has */ 14 #define CS_CNT 2 15 16 struct renesas_dbsc5_board_config { 17 /* Channels in use */ 18 u8 bdcfg_phyvalid; 19 /* Read vref (SoC) training range */ 20 u32 bdcfg_vref_r; 21 /* Write vref (MR14, MR15) training range */ 22 u16 bdcfg_vref_w; 23 /* CA vref (MR12) training range */ 24 u16 bdcfg_vref_ca; 25 /* RFM required check */ 26 bool bdcfg_rfm_chk; 27 28 /* Board parameter about channels */ 29 struct { 30 /* 31 * 0x00: 4Gb dual channel die / 2Gb single channel die 32 * 0x01: 6Gb dual channel die / 3Gb single channel die 33 * 0x02: 8Gb dual channel die / 4Gb single channel die 34 * 0x03: 12Gb dual channel die / 6Gb single channel die 35 * 0x04: 16Gb dual channel die / 8Gb single channel die 36 * 0x05: 24Gb dual channel die / 12Gb single channel die 37 * 0x06: 32Gb dual channel die / 16Gb single channel die 38 * 0x07: 24Gb single channel die 39 * 0x08: 32Gb single channel die 40 * 0xFF: NO_MEMORY 41 */ 42 u8 bdcfg_ddr_density[CS_CNT]; 43 /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ 44 u32 bdcfg_ca_swap; 45 /* SoC dqsX([1][0]) -> MEM dqsY: */ 46 u8 bdcfg_dqs_swap; 47 /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ 48 u32 bdcfg_dq_swap[SLICE_CNT]; 49 /* SoC dm -> MEM dqY/dm: (8 means DM) */ 50 u8 bdcfg_dm_swap[SLICE_CNT]; 51 /* SoC ckeX([1][0]) -> MEM csY */ 52 u8 bdcfg_cs_swap; 53 } ch[4]; 54 }; 55 56 #endif /* __INCLUDE_DBSC5_H__ */ 57