1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2008-2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef _DDR_SPD_H_ 7 #define _DDR_SPD_H_ 8 9 #include <linux/types.h> 10 11 /* 12 * Format from "JEDEC Standard No. 21-C, 13 * Appendix D: Rev 1.0: SPD's for DDR SDRAM 14 */ 15 typedef struct ddr1_spd_eeprom_s { 16 unsigned char info_size; /* 0 # bytes written into serial memory */ 17 unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ 18 unsigned char mem_type; /* 2 Fundamental memory type */ 19 unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ 20 unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ 21 unsigned char nrows; /* 5 Number of DIMM Banks */ 22 unsigned char dataw_lsb; /* 6 Data Width of this assembly */ 23 unsigned char dataw_msb; /* 7 ... Data Width continuation */ 24 unsigned char voltage; /* 8 Voltage intf std of this assembly */ 25 unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ 26 unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ 27 unsigned char config; /* 11 DIMM Configuration type */ 28 unsigned char refresh; /* 12 Refresh Rate/Type */ 29 unsigned char primw; /* 13 Primary SDRAM Width */ 30 unsigned char ecw; /* 14 Error Checking SDRAM width */ 31 unsigned char min_delay; /* 15 for Back to Back Random Address */ 32 unsigned char burstl; /* 16 Burst Lengths Supported */ 33 unsigned char nbanks; /* 17 # of Banks on SDRAM Device */ 34 unsigned char cas_lat; /* 18 CAS# Latencies Supported */ 35 unsigned char cs_lat; /* 19 CS# Latency */ 36 unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ 37 unsigned char mod_attr; /* 21 SDRAM Module Attributes */ 38 unsigned char dev_attr; /* 22 SDRAM Device Attributes */ 39 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */ 40 unsigned char clk_access2; /* 24 SDRAM Access from 41 Clk @ CL=X-0.5 (tAC) */ 42 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */ 43 unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */ 44 unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ 45 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ 46 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ 47 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ 48 unsigned char bank_dens; /* 31 Density of each bank on module */ 49 unsigned char ca_setup; /* 32 Addr + Cmd Setup Time Before Clk */ 50 unsigned char ca_hold; /* 33 Addr + Cmd Hold Time After Clk */ 51 unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */ 52 unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */ 53 unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */ 54 unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ 55 unsigned char trfc; /* 42 Min Auto to Active period tRFC */ 56 unsigned char tckmax; /* 43 Max device cycle time tCKmax */ 57 unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ 58 unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ 59 unsigned char res_46; /* 46 Reserved */ 60 unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */ 61 unsigned char res_48_61[14]; /* 48-61 Reserved */ 62 unsigned char spd_rev; /* 62 SPD Data Revision Code */ 63 unsigned char cksum; /* 63 Checksum for bytes 0-62 */ 64 unsigned char mid[8]; /* 64-71 Mfr's JEDEC ID code per JEP-106 */ 65 unsigned char mloc; /* 72 Manufacturing Location */ 66 unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ 67 unsigned char rev[2]; /* 91 Revision Code */ 68 unsigned char mdate[2]; /* 93 Manufacturing Date */ 69 unsigned char sernum[4]; /* 95 Assembly Serial Number */ 70 unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ 71 72 } ddr1_spd_eeprom_t; 73 74 /* 75 * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM", 76 * SPD Revision 1.2 77 */ 78 typedef struct ddr2_spd_eeprom_s { 79 unsigned char info_size; /* 0 # bytes written into serial memory */ 80 unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ 81 unsigned char mem_type; /* 2 Fundamental memory type */ 82 unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ 83 unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ 84 unsigned char mod_ranks; /* 5 Number of DIMM Ranks */ 85 unsigned char dataw; /* 6 Module Data Width */ 86 unsigned char res_7; /* 7 Reserved */ 87 unsigned char voltage; /* 8 Voltage intf std of this assembly */ 88 unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ 89 unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ 90 unsigned char config; /* 11 DIMM Configuration type */ 91 unsigned char refresh; /* 12 Refresh Rate/Type */ 92 unsigned char primw; /* 13 Primary SDRAM Width */ 93 unsigned char ecw; /* 14 Error Checking SDRAM width */ 94 unsigned char res_15; /* 15 Reserved */ 95 unsigned char burstl; /* 16 Burst Lengths Supported */ 96 unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ 97 unsigned char cas_lat; /* 18 CAS# Latencies Supported */ 98 unsigned char mech_char; /* 19 DIMM Mechanical Characteristics */ 99 unsigned char dimm_type; /* 20 DIMM type information */ 100 unsigned char mod_attr; /* 21 SDRAM Module Attributes */ 101 unsigned char dev_attr; /* 22 SDRAM Device Attributes */ 102 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */ 103 unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */ 104 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */ 105 unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */ 106 unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ 107 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ 108 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ 109 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ 110 unsigned char rank_dens; /* 31 Density of each rank on module */ 111 unsigned char ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */ 112 unsigned char ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */ 113 unsigned char data_setup; /* 34 Data Input Setup Time 114 Before Strobe (tDS) */ 115 unsigned char data_hold; /* 35 Data Input Hold Time 116 After Strobe (tDH) */ 117 unsigned char twr; /* 36 Write Recovery time tWR */ 118 unsigned char twtr; /* 37 Int write to read delay tWTR */ 119 unsigned char trtp; /* 38 Int read to precharge delay tRTP */ 120 unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ 121 unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ 122 unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ 123 unsigned char trfc; /* 42 Min Auto to Active period tRFC */ 124 unsigned char tckmax; /* 43 Max device cycle time tCKmax */ 125 unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ 126 unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ 127 unsigned char pll_relock; /* 46 PLL Relock time */ 128 unsigned char t_casemax; /* 47 Tcasemax */ 129 unsigned char psi_ta_dram; /* 48 Thermal Resistance of DRAM Package from 130 Top (Case) to Ambient (Psi T-A DRAM) */ 131 unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient 132 due to Activate-Precharge/Mode Bits 133 (DT0/Mode Bits) */ 134 unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient 135 due to Precharge/Quiet Standby 136 (DT2N/DT2Q) */ 137 unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient 138 due to Precharge Power-Down (DT2P) */ 139 unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient 140 due to Active Standby (DT3N) */ 141 unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient 142 due to Active Power-Down with 143 Fast PDN Exit (DT3Pfast) */ 144 unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient 145 due to Active Power-Down with Slow 146 PDN Exit (DT3Pslow) */ 147 unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient 148 due to Page Open Burst Read/DT4R4W 149 Mode Bit (DT4R/DT4R4W Mode Bit) */ 150 unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient 151 due to Burst Refresh (DT5B) */ 152 unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient 153 due to Bank Interleave Reads with 154 Auto-Precharge (DT7) */ 155 unsigned char psi_ta_pll; /* 58 Thermal Resistance of PLL Package form 156 Top (Case) to Ambient (Psi T-A PLL) */ 157 unsigned char psi_ta_reg; /* 59 Thermal Reisitance of Register Package 158 from Top (Case) to Ambient 159 (Psi T-A Register) */ 160 unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient 161 due to PLL Active (DT PLL Active) */ 162 unsigned char dtregact; /* 61 Register Case Temperature Rise from 163 Ambient due to Register Active/Mode Bit 164 (DT Register Active/Mode Bit) */ 165 unsigned char spd_rev; /* 62 SPD Data Revision Code */ 166 unsigned char cksum; /* 63 Checksum for bytes 0-62 */ 167 unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */ 168 unsigned char mloc; /* 72 Manufacturing Location */ 169 unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ 170 unsigned char rev[2]; /* 91 Revision Code */ 171 unsigned char mdate[2]; /* 93 Manufacturing Date */ 172 unsigned char sernum[4]; /* 95 Assembly Serial Number */ 173 unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ 174 175 } ddr2_spd_eeprom_t; 176 177 typedef struct ddr3_spd_eeprom_s { 178 /* General Section: Bytes 0-59 */ 179 unsigned char info_size_crc; /* 0 # bytes written into serial memory, 180 CRC coverage */ 181 unsigned char spd_rev; /* 1 Total # bytes of SPD mem device */ 182 unsigned char mem_type; /* 2 Key Byte / Fundamental mem type */ 183 unsigned char module_type; /* 3 Key Byte / Module Type */ 184 unsigned char density_banks; /* 4 SDRAM Density and Banks */ 185 unsigned char addressing; /* 5 SDRAM Addressing */ 186 unsigned char module_vdd; /* 6 Module nominal voltage, VDD */ 187 unsigned char organization; /* 7 Module Organization */ 188 unsigned char bus_width; /* 8 Module Memory Bus Width */ 189 unsigned char ftb_div; /* 9 Fine Timebase (FTB) 190 Dividend / Divisor */ 191 unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */ 192 unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */ 193 unsigned char tck_min; /* 12 SDRAM Minimum Cycle Time */ 194 unsigned char res_13; /* 13 Reserved */ 195 unsigned char caslat_lsb; /* 14 CAS Latencies Supported, 196 Least Significant Byte */ 197 unsigned char caslat_msb; /* 15 CAS Latencies Supported, 198 Most Significant Byte */ 199 unsigned char taa_min; /* 16 Min CAS Latency Time */ 200 unsigned char twr_min; /* 17 Min Write REcovery Time */ 201 unsigned char trcd_min; /* 18 Min RAS# to CAS# Delay Time */ 202 unsigned char trrd_min; /* 19 Min Row Active to 203 Row Active Delay Time */ 204 unsigned char trp_min; /* 20 Min Row Precharge Delay Time */ 205 unsigned char tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */ 206 unsigned char tras_min_lsb; /* 22 Min Active to Precharge 207 Delay Time */ 208 unsigned char trc_min_lsb; /* 23 Min Active to Active/Refresh 209 Delay Time, LSB */ 210 unsigned char trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */ 211 unsigned char trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */ 212 unsigned char twtr_min; /* 26 Min Internal Write to 213 Read Command Delay Time */ 214 unsigned char trtp_min; /* 27 Min Internal Read to Precharge 215 Command Delay Time */ 216 unsigned char tfaw_msb; /* 28 Upper Nibble for tFAW */ 217 unsigned char tfaw_min; /* 29 Min Four Activate Window 218 Delay Time*/ 219 unsigned char opt_features; /* 30 SDRAM Optional Features */ 220 unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ 221 unsigned char therm_sensor; /* 32 Module Thermal Sensor */ 222 unsigned char device_type; /* 33 SDRAM device type */ 223 int8_t fine_tck_min; /* 34 Fine offset for tCKmin */ 224 int8_t fine_taa_min; /* 35 Fine offset for tAAmin */ 225 int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */ 226 int8_t fine_trp_min; /* 37 Fine offset for tRPmin */ 227 int8_t fine_trc_min; /* 38 Fine offset for tRCmin */ 228 unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */ 229 230 /* Module-Specific Section: Bytes 60-116 */ 231 union { 232 struct { 233 /* 60 (Unbuffered) Module Nominal Height */ 234 unsigned char mod_height; 235 /* 61 (Unbuffered) Module Maximum Thickness */ 236 unsigned char mod_thickness; 237 /* 62 (Unbuffered) Reference Raw Card Used */ 238 unsigned char ref_raw_card; 239 /* 63 (Unbuffered) Address Mapping from 240 Edge Connector to DRAM */ 241 unsigned char addr_mapping; 242 /* 64-116 (Unbuffered) Reserved */ 243 unsigned char res_64_116[53]; 244 } unbuffered; 245 struct { 246 /* 60 (Registered) Module Nominal Height */ 247 unsigned char mod_height; 248 /* 61 (Registered) Module Maximum Thickness */ 249 unsigned char mod_thickness; 250 /* 62 (Registered) Reference Raw Card Used */ 251 unsigned char ref_raw_card; 252 /* 63 DIMM Module Attributes */ 253 unsigned char modu_attr; 254 /* 64 RDIMM Thermal Heat Spreader Solution */ 255 unsigned char thermal; 256 /* 65 Register Manufacturer ID Code, Least Significant Byte */ 257 unsigned char reg_id_lo; 258 /* 66 Register Manufacturer ID Code, Most Significant Byte */ 259 unsigned char reg_id_hi; 260 /* 67 Register Revision Number */ 261 unsigned char reg_rev; 262 /* 68 Register Type */ 263 unsigned char reg_type; 264 /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */ 265 unsigned char rcw[8]; 266 } registered; 267 unsigned char uc[57]; /* 60-116 Module-Specific Section */ 268 } mod_section; 269 270 /* Unique Module ID: Bytes 117-125 */ 271 unsigned char mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */ 272 unsigned char mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */ 273 unsigned char mloc; /* 119 Mfg Location */ 274 unsigned char mdate[2]; /* 120-121 Mfg Date */ 275 unsigned char sernum[4]; /* 122-125 Module Serial Number */ 276 277 /* CRC: Bytes 126-127 */ 278 unsigned char crc[2]; /* 126-127 SPD CRC */ 279 280 /* Other Manufacturer Fields and User Space: Bytes 128-255 */ 281 unsigned char mpart[18]; /* 128-145 Mfg's Module Part Number */ 282 unsigned char mrev[2]; /* 146-147 Module Revision Code */ 283 284 unsigned char dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */ 285 unsigned char dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */ 286 287 unsigned char msd[26]; /* 150-175 Mfg's Specific Data */ 288 unsigned char cust[80]; /* 176-255 Open for Customer Use */ 289 290 } ddr3_spd_eeprom_t; 291 292 /* From JEEC Standard No. 21-C release 23A */ 293 struct ddr4_spd_eeprom_s { 294 /* General Section: Bytes 0-127 */ 295 uint8_t info_size_crc; /* 0 # bytes */ 296 uint8_t spd_rev; /* 1 Total # bytes of SPD */ 297 uint8_t mem_type; /* 2 Key Byte / mem type */ 298 uint8_t module_type; /* 3 Key Byte / Module Type */ 299 uint8_t density_banks; /* 4 Density and Banks */ 300 uint8_t addressing; /* 5 Addressing */ 301 uint8_t package_type; /* 6 Package type */ 302 uint8_t opt_feature; /* 7 Optional features */ 303 uint8_t thermal_ref; /* 8 Thermal and refresh */ 304 uint8_t oth_opt_features; /* 9 Other optional features */ 305 uint8_t res_10; /* 10 Reserved */ 306 uint8_t module_vdd; /* 11 Module nominal voltage */ 307 uint8_t organization; /* 12 Module Organization */ 308 uint8_t bus_width; /* 13 Module Memory Bus Width */ 309 uint8_t therm_sensor; /* 14 Module Thermal Sensor */ 310 uint8_t ext_type; /* 15 Extended module type */ 311 uint8_t res_16; 312 uint8_t timebases; /* 17 MTb and FTB */ 313 uint8_t tck_min; /* 18 tCKAVGmin */ 314 uint8_t tck_max; /* 19 TCKAVGmax */ 315 uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */ 316 uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */ 317 uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */ 318 uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */ 319 uint8_t taa_min; /* 24 Min CAS Latency Time */ 320 uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */ 321 uint8_t trp_min; /* 26 Min Row Precharge Delay Time */ 322 uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */ 323 uint8_t tras_min_lsb; /* 28 tRASmin, lsb */ 324 uint8_t trc_min_lsb; /* 29 tRCmin, lsb */ 325 uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */ 326 uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */ 327 uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */ 328 uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */ 329 uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */ 330 uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */ 331 uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */ 332 uint8_t tfaw_min; /* 37 tFAW, lsb */ 333 uint8_t trrds_min; /* 38 tRRD_Smin, MTB */ 334 uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */ 335 uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */ 336 uint8_t res_41[60-41]; /* 41 Rserved */ 337 uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ 338 uint8_t res_78[117-78]; /* 78~116, Reserved */ 339 int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */ 340 int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */ 341 int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */ 342 int8_t fine_trc_min; /* 120 Fine offset for tRCmin */ 343 int8_t fine_trp_min; /* 121 Fine offset for tRPmin */ 344 int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */ 345 int8_t fine_taa_min; /* 123 Fine offset for tAAmin */ 346 int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */ 347 int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */ 348 /* CRC: Bytes 126-127 */ 349 uint8_t crc[2]; /* 126-127 SPD CRC */ 350 351 /* Module-Specific Section: Bytes 128-255 */ 352 union { 353 struct { 354 /* 128 (Unbuffered) Module Nominal Height */ 355 uint8_t mod_height; 356 /* 129 (Unbuffered) Module Maximum Thickness */ 357 uint8_t mod_thickness; 358 /* 130 (Unbuffered) Reference Raw Card Used */ 359 uint8_t ref_raw_card; 360 /* 131 (Unbuffered) Address Mapping from 361 Edge Connector to DRAM */ 362 uint8_t addr_mapping; 363 /* 132~253 (Unbuffered) Reserved */ 364 uint8_t res_132[254-132]; 365 /* 254~255 CRC */ 366 uint8_t crc[2]; 367 } unbuffered; 368 struct { 369 /* 128 (Registered) Module Nominal Height */ 370 uint8_t mod_height; 371 /* 129 (Registered) Module Maximum Thickness */ 372 uint8_t mod_thickness; 373 /* 130 (Registered) Reference Raw Card Used */ 374 uint8_t ref_raw_card; 375 /* 131 DIMM Module Attributes */ 376 uint8_t modu_attr; 377 /* 132 RDIMM Thermal Heat Spreader Solution */ 378 uint8_t thermal; 379 /* 133 Register Manufacturer ID Code, LSB */ 380 uint8_t reg_id_lo; 381 /* 134 Register Manufacturer ID Code, MSB */ 382 uint8_t reg_id_hi; 383 /* 135 Register Revision Number */ 384 uint8_t reg_rev; 385 /* 136 Address mapping from register to DRAM */ 386 u8 reg_map; 387 u8 ca_stren; 388 u8 clk_stren; 389 /* 139~253 Reserved */ 390 u8 res_137[254 - 139]; 391 /* 254~255 CRC */ 392 uint8_t crc[2]; 393 } registered; 394 struct { 395 /* 128 (Loadreduced) Module Nominal Height */ 396 uint8_t mod_height; 397 /* 129 (Loadreduced) Module Maximum Thickness */ 398 uint8_t mod_thickness; 399 /* 130 (Loadreduced) Reference Raw Card Used */ 400 uint8_t ref_raw_card; 401 /* 131 DIMM Module Attributes */ 402 uint8_t modu_attr; 403 /* 132 RDIMM Thermal Heat Spreader Solution */ 404 uint8_t thermal; 405 /* 133 Register Manufacturer ID Code, LSB */ 406 uint8_t reg_id_lo; 407 /* 134 Register Manufacturer ID Code, MSB */ 408 uint8_t reg_id_hi; 409 /* 135 Register Revision Number */ 410 uint8_t reg_rev; 411 /* 136 Address mapping from register to DRAM */ 412 uint8_t reg_map; 413 /* 137 Register Output Drive Strength for CMD/Add*/ 414 uint8_t reg_drv; 415 /* 138 Register Output Drive Strength for CK */ 416 uint8_t reg_drv_ck; 417 /* 139 Data Buffer Revision Number */ 418 uint8_t data_buf_rev; 419 /* 140 DRAM VrefDQ for Package Rank 0 */ 420 uint8_t vrefqe_r0; 421 /* 141 DRAM VrefDQ for Package Rank 1 */ 422 uint8_t vrefqe_r1; 423 /* 142 DRAM VrefDQ for Package Rank 2 */ 424 uint8_t vrefqe_r2; 425 /* 143 DRAM VrefDQ for Package Rank 3 */ 426 uint8_t vrefqe_r3; 427 /* 144 Data Buffer VrefDQ for DRAM Interface */ 428 uint8_t data_intf; 429 /* 430 * 145 Data Buffer MDQ Drive Strength and RTT 431 * for data rate <= 1866 432 */ 433 uint8_t data_drv_1866; 434 /* 435 * 146 Data Buffer MDQ Drive Strength and RTT 436 * for 1866 < data rate <= 2400 437 */ 438 uint8_t data_drv_2400; 439 /* 440 * 147 Data Buffer MDQ Drive Strength and RTT 441 * for 2400 < data rate <= 3200 442 */ 443 uint8_t data_drv_3200; 444 /* 148 DRAM Drive Strength */ 445 uint8_t dram_drv; 446 /* 447 * 149 DRAM ODT (RTT_WR, RTT_NOM) 448 * for data rate <= 1866 449 */ 450 uint8_t dram_odt_1866; 451 /* 452 * 150 DRAM ODT (RTT_WR, RTT_NOM) 453 * for 1866 < data rate <= 2400 454 */ 455 uint8_t dram_odt_2400; 456 /* 457 * 151 DRAM ODT (RTT_WR, RTT_NOM) 458 * for 2400 < data rate <= 3200 459 */ 460 uint8_t dram_odt_3200; 461 /* 462 * 152 DRAM ODT (RTT_PARK) 463 * for data rate <= 1866 464 */ 465 uint8_t dram_odt_park_1866; 466 /* 467 * 153 DRAM ODT (RTT_PARK) 468 * for 1866 < data rate <= 2400 469 */ 470 uint8_t dram_odt_park_2400; 471 /* 472 * 154 DRAM ODT (RTT_PARK) 473 * for 2400 < data rate <= 3200 474 */ 475 uint8_t dram_odt_park_3200; 476 uint8_t res_155[254-155]; /* Reserved */ 477 /* 254~255 CRC */ 478 uint8_t crc[2]; 479 } loadreduced; 480 uint8_t uc[128]; /* 128-255 Module-Specific Section */ 481 } mod_section; 482 483 uint8_t res_256[320-256]; /* 256~319 Reserved */ 484 485 /* Module supplier's data: Byte 320~383 */ 486 uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */ 487 uint8_t mmid_msb; /* 321 Module MfgID Code MSB */ 488 uint8_t mloc; /* 322 Mfg Location */ 489 uint8_t mdate[2]; /* 323~324 Mfg Date */ 490 uint8_t sernum[4]; /* 325~328 Module Serial Number */ 491 uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */ 492 uint8_t mrev; /* 349 Module Revision Code */ 493 uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */ 494 uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */ 495 uint8_t stepping; /* 352 DRAM stepping */ 496 uint8_t msd[29]; /* 353~381 Mfg's Specific Data */ 497 uint8_t res_382[2]; /* 382~383 Reserved */ 498 499 uint8_t user[512-384]; /* 384~511 End User Programmable */ 500 }; 501 502 extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd); 503 extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd); 504 extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd); 505 extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd); 506 extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); 507 unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd); 508 509 /* 510 * Byte 2 Fundamental Memory Types. 511 */ 512 #define SPD_MEMTYPE_FPM (0x01) 513 #define SPD_MEMTYPE_EDO (0x02) 514 #define SPD_MEMTYPE_PIPE_NIBBLE (0x03) 515 #define SPD_MEMTYPE_SDRAM (0x04) 516 #define SPD_MEMTYPE_ROM (0x05) 517 #define SPD_MEMTYPE_SGRAM (0x06) 518 #define SPD_MEMTYPE_DDR (0x07) 519 #define SPD_MEMTYPE_DDR2 (0x08) 520 #define SPD_MEMTYPE_DDR2_FBDIMM (0x09) 521 #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) 522 #define SPD_MEMTYPE_DDR3 (0x0B) 523 #define SPD_MEMTYPE_DDR4 (0x0C) 524 525 /* DIMM Type for DDR2 SPD (according to v1.3) */ 526 #define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00) 527 #define DDR2_SPD_DIMMTYPE_RDIMM (0x01) 528 #define DDR2_SPD_DIMMTYPE_UDIMM (0x02) 529 #define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04) 530 #define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06) 531 #define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07) 532 #define DDR2_SPD_DIMMTYPE_MICRO_DIMM (0x08) 533 #define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10) 534 #define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20) 535 536 /* Byte 3 Key Byte / Module Type for DDR3 SPD */ 537 #define DDR3_SPD_MODULETYPE_MASK (0x0f) 538 #define DDR3_SPD_MODULETYPE_RDIMM (0x01) 539 #define DDR3_SPD_MODULETYPE_UDIMM (0x02) 540 #define DDR3_SPD_MODULETYPE_SO_DIMM (0x03) 541 #define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04) 542 #define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05) 543 #define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06) 544 #define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07) 545 #define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08) 546 #define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09) 547 #define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0A) 548 #define DDR3_SPD_MODULETYPE_LRDIMM (0x0B) 549 #define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C) 550 #define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D) 551 552 /* DIMM Type for DDR4 SPD */ 553 #define DDR4_SPD_MODULETYPE_MASK (0x0f) 554 #define DDR4_SPD_MODULETYPE_EXT (0x00) 555 #define DDR4_SPD_MODULETYPE_RDIMM (0x01) 556 #define DDR4_SPD_MODULETYPE_UDIMM (0x02) 557 #define DDR4_SPD_MODULETYPE_SO_DIMM (0x03) 558 #define DDR4_SPD_MODULETYPE_LRDIMM (0x04) 559 #define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05) 560 #define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06) 561 #define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08) 562 #define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09) 563 #define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C) 564 #define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D) 565 566 #endif /* _DDR_SPD_H_ */ 567