1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * (C) Copyright 2022 - Analog Devices, Inc. 4 * 5 * Written and/or maintained by Timesys Corporation 6 * 7 * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> 8 * Contact: Greg Malysa <greg.malysa@timesys.com> 9 * 10 */ 11 12 #ifndef DT_BINDINGS_CLOCK_ADI_SC5XX_CLOCK_H 13 #define DT_BINDINGS_CLOCK_ADI_SC5XX_CLOCK_H 14 15 //ADSP-SC594 16 #define ADSP_SC594_CLK_DUMMY 0 17 #define ADSP_SC594_CLK_SYS_CLKIN0 1 18 #define ADSP_SC594_CLK_SYS_CLKIN1 2 19 #define ADSP_SC594_CLK_CGU1_IN 3 20 #define ADSP_SC594_CLK_CGU0_PLL_IN 4 21 #define ADSP_SC594_CLK_CGU1_PLL_IN 5 22 #define ADSP_SC594_CLK_CGU0_VCO_OUT 6 23 #define ADSP_SC594_CLK_CGU1_VCO_OUT 7 24 #define ADSP_SC594_CLK_CGU0_PLLCLK 8 25 #define ADSP_SC594_CLK_CGU1_PLLCLK 9 26 #define ADSP_SC594_CLK_CGU0_CDIV 10 27 #define ADSP_SC594_CLK_CGU0_SYSCLK 11 28 #define ADSP_SC594_CLK_CGU0_DDIV 12 29 #define ADSP_SC594_CLK_CGU0_ODIV 13 30 #define ADSP_SC594_CLK_CGU0_S0SELDIV 14 31 #define ADSP_SC594_CLK_CGU0_S1SELDIV 15 32 #define ADSP_SC594_CLK_CGU0_S1SELEXDIV 16 33 #define ADSP_SC594_CLK_CGU0_S1SEL 17 34 #define ADSP_SC594_CLK_CGU1_CDIV 18 35 #define ADSP_SC594_CLK_CGU1_SYSCLK 19 36 #define ADSP_SC594_CLK_CGU1_DDIV 20 37 #define ADSP_SC594_CLK_CGU1_ODIV 21 38 #define ADSP_SC594_CLK_CGU1_S0SELDIV 22 39 #define ADSP_SC594_CLK_CGU1_S1SELDIV 23 40 #define ADSP_SC594_CLK_CGU1_S1SELEXDIV 24 41 #define ADSP_SC594_CLK_CGU1_S1SEL 25 42 #define ADSP_SC594_CLK_CGU0_CCLK0 26 43 #define ADSP_SC594_CLK_CGU0_CCLK1 27 44 #define ADSP_SC594_CLK_CGU0_OCLK 28 45 #define ADSP_SC594_CLK_CGU0_DCLK 29 46 #define ADSP_SC594_CLK_CGU0_SCLK1 30 47 #define ADSP_SC594_CLK_CGU0_SCLK0 31 48 #define ADSP_SC594_CLK_CGU1_CCLK0 32 49 #define ADSP_SC594_CLK_CGU1_CCLK1 33 50 #define ADSP_SC594_CLK_CGU1_OCLK 34 51 #define ADSP_SC594_CLK_CGU1_DCLK 35 52 #define ADSP_SC594_CLK_CGU1_SCLK1 36 53 #define ADSP_SC594_CLK_CGU1_SCLK0 37 54 #define ADSP_SC594_CLK_SHARC0_SEL 38 55 #define ADSP_SC594_CLK_SHARC1_SEL 39 56 #define ADSP_SC594_CLK_ARM_SEL 40 57 #define ADSP_SC594_CLK_CDU_DDR_SEL 41 58 #define ADSP_SC594_CLK_CAN_SEL 42 59 #define ADSP_SC594_CLK_SPDIF_SEL 43 60 #define ADSP_SC594_CLK_RESERVED_SEL 44 61 #define ADSP_SC594_CLK_GIGE_SEL 45 62 #define ADSP_SC594_CLK_LP_SEL 46 63 #define ADSP_SC594_CLK_LPDDR_SEL 47 64 #define ADSP_SC594_CLK_OSPI_SEL 48 65 #define ADSP_SC594_CLK_TRACE_SEL 49 66 #define ADSP_SC594_CLK_SHARC0 50 67 #define ADSP_SC594_CLK_SHARC1 51 68 #define ADSP_SC594_CLK_ARM 52 69 #define ADSP_SC594_CLK_CDU_DDR 53 70 #define ADSP_SC594_CLK_CAN 54 71 #define ADSP_SC594_CLK_SPDIF 55 72 #define ADSP_SC594_CLK_SPI 56 73 #define ADSP_SC594_CLK_GIGE 57 74 #define ADSP_SC594_CLK_LP 58 75 #define ADSP_SC594_CLK_LPDDR 59 76 #define ADSP_SC594_CLK_OSPI 60 77 #define ADSP_SC594_CLK_TRACE 61 78 #define ADSP_SC594_CLK_END 62 79 80 //ADSP-SC598 81 #define ADSP_SC598_CLK_DUMMY 0 82 #define ADSP_SC598_CLK_SYS_CLKIN0 1 83 #define ADSP_SC598_CLK_SYS_CLKIN1 2 84 #define ADSP_SC598_CLK_CGU0_PLL_IN 3 85 #define ADSP_SC598_CLK_CGU0_VCO_OUT 4 86 #define ADSP_SC598_CLK_CGU0_PLLCLK 5 87 #define ADSP_SC598_CLK_CGU1_IN 6 88 #define ADSP_SC598_CLK_CGU1_PLL_IN 7 89 #define ADSP_SC598_CLK_CGU1_VCO_OUT 8 90 #define ADSP_SC598_CLK_CGU1_PLLCLK 9 91 #define ADSP_SC598_CLK_CGU0_CDIV 10 92 #define ADSP_SC598_CLK_CGU0_SYSCLK 11 93 #define ADSP_SC598_CLK_CGU0_DDIV 12 94 #define ADSP_SC598_CLK_CGU0_ODIV 13 95 #define ADSP_SC598_CLK_CGU0_S0SELDIV 14 96 #define ADSP_SC598_CLK_CGU0_S1SELDIV 15 97 #define ADSP_SC598_CLK_CGU0_S1SELEXDIV 16 98 #define ADSP_SC598_CLK_CGU0_S1SEL 17 99 #define ADSP_SC598_CLK_CGU1_CDIV 18 100 #define ADSP_SC598_CLK_CGU1_SYSCLK 19 101 #define ADSP_SC598_CLK_CGU1_DDIV 20 102 #define ADSP_SC598_CLK_CGU1_ODIV 21 103 #define ADSP_SC598_CLK_CGU1_S0SELDIV 22 104 #define ADSP_SC598_CLK_CGU1_S1SELDIV 23 105 #define ADSP_SC598_CLK_CGU1_S0SELEXDIV 24 106 #define ADSP_SC598_CLK_CGU1_S1SELEXDIV 25 107 #define ADSP_SC598_CLK_CGU1_S0SEL 26 108 #define ADSP_SC598_CLK_CGU1_S1SEL 27 109 #define ADSP_SC598_CLK_CGU0_CCLK2 28 110 #define ADSP_SC598_CLK_CGU0_CCLK0 29 111 #define ADSP_SC598_CLK_CGU0_OCLK 30 112 #define ADSP_SC598_CLK_CGU0_DCLK 31 113 #define ADSP_SC598_CLK_CGU0_SCLK1 32 114 #define ADSP_SC598_CLK_CGU0_SCLK0 33 115 #define ADSP_SC598_CLK_CGU1_CCLK0 34 116 #define ADSP_SC598_CLK_CGU1_OCLK 35 117 #define ADSP_SC598_CLK_CGU1_DCLK 36 118 #define ADSP_SC598_CLK_CGU1_SCLK1 37 119 #define ADSP_SC598_CLK_CGU1_SCLK0 38 120 #define ADSP_SC598_CLK_CGU1_CCLK2 39 121 #define ADSP_SC598_CLK_DCLK0_HALF 40 122 #define ADSP_SC598_CLK_DCLK1_HALF 41 123 #define ADSP_SC598_CLK_CGU1_SCLK1_HALF 42 124 #define ADSP_SC598_CLK_SHARC0_SEL 43 125 #define ADSP_SC598_CLK_SHARC1_SEL 44 126 #define ADSP_SC598_CLK_ARM_SEL 45 127 #define ADSP_SC598_CLK_CDU_DDR_SEL 46 128 #define ADSP_SC598_CLK_CAN_SEL 47 129 #define ADSP_SC598_CLK_SPDIF_SEL 48 130 #define ADSP_SC598_CLK_SPI_SEL 49 131 #define ADSP_SC598_CLK_GIGE_SEL 50 132 #define ADSP_SC598_CLK_LP_SEL 51 133 #define ADSP_SC598_CLK_LP_DDR_SEL 52 134 #define ADSP_SC598_CLK_OSPI_REFCLK_SEL 53 135 #define ADSP_SC598_CLK_TRACE_SEL 54 136 #define ADSP_SC598_CLK_EMMC_SEL 55 137 #define ADSP_SC598_CLK_EMMC_TIMER_QMC_SEL 56 138 #define ADSP_SC598_CLK_SHARC0 57 139 #define ADSP_SC598_CLK_SHARC1 58 140 #define ADSP_SC598_CLK_ARM 59 141 #define ADSP_SC598_CLK_CDU_DDR 60 142 #define ADSP_SC598_CLK_CAN 61 143 #define ADSP_SC598_CLK_SPDIF 62 144 #define ADSP_SC598_CLK_SPI 63 145 #define ADSP_SC598_CLK_GIGE 64 146 #define ADSP_SC598_CLK_LP 65 147 #define ADSP_SC598_CLK_LP_DDR 66 148 #define ADSP_SC598_CLK_OSPI_REFCLK 67 149 #define ADSP_SC598_CLK_TRACE 68 150 #define ADSP_SC598_CLK_EMMC 69 151 #define ADSP_SC598_CLK_EMMC_TIMER_QMC 70 152 #define ADSP_SC598_CLK_3PLL_PLL_IN 71 153 #define ADSP_SC598_CLK_3PLL_VCO_OUT 72 154 #define ADSP_SC598_CLK_3PLL_PLLCLK 73 155 #define ADSP_SC598_CLK_3PLL_DDIV 74 156 #define ADSP_SC598_CLK_DDR 75 157 #define ADSP_SC598_CLK_END 76 158 159 //ADSP-SC58X 160 #define ADSP_SC58X_CLK_DUMMY 0 161 #define ADSP_SC58X_CLK_SYS_CLKIN0 1 162 #define ADSP_SC58X_CLK_SYS_CLKIN1 2 163 #define ADSP_SC58X_CLK_CGU0_PLL_IN 3 164 #define ADSP_SC58X_CLK_CGU0_VCO_OUT 4 165 #define ADSP_SC58X_CLK_CGU0_PLLCLK 5 166 #define ADSP_SC58X_CLK_CGU1_IN 6 167 #define ADSP_SC58X_CLK_CGU1_PLL_IN 7 168 #define ADSP_SC58X_CLK_CGU1_VCO_OUT 8 169 #define ADSP_SC58X_CLK_CGU1_PLLCLK 9 170 #define ADSP_SC58X_CLK_CGU0_CDIV 10 171 #define ADSP_SC58X_CLK_CGU0_SYSCLK 11 172 #define ADSP_SC58X_CLK_CGU0_DDIV 12 173 #define ADSP_SC58X_CLK_CGU0_ODIV 13 174 #define ADSP_SC58X_CLK_CGU0_S0SELDIV 14 175 #define ADSP_SC58X_CLK_CGU0_S1SELDIV 15 176 #define ADSP_SC58X_CLK_CGU1_CDIV 16 177 #define ADSP_SC58X_CLK_CGU1_SYSCLK 17 178 #define ADSP_SC58X_CLK_CGU1_DDIV 18 179 #define ADSP_SC58X_CLK_CGU1_ODIV 19 180 #define ADSP_SC58X_CLK_CGU1_S0SELDIV 20 181 #define ADSP_SC58X_CLK_CGU1_S1SELDIV 21 182 #define ADSP_SC58X_CLK_CGU0_CCLK0 22 183 #define ADSP_SC58X_CLK_CGU0_CCLK1 23 184 #define ADSP_SC58X_CLK_CGU0_OCLK 24 185 #define ADSP_SC58X_CLK_CGU0_DCLK 25 186 #define ADSP_SC58X_CLK_CGU0_SCLK1 26 187 #define ADSP_SC58X_CLK_CGU0_SCLK0 27 188 #define ADSP_SC58X_CLK_CGU1_CCLK0 28 189 #define ADSP_SC58X_CLK_CGU1_CCLK1 29 190 #define ADSP_SC58X_CLK_CGU1_OCLK 30 191 #define ADSP_SC58X_CLK_CGU1_DCLK 31 192 #define ADSP_SC58X_CLK_CGU1_SCLK1 32 193 #define ADSP_SC58X_CLK_CGU1_SCLK0 33 194 #define ADSP_SC58X_CLK_OCLK0_HALF 34 195 #define ADSP_SC58X_CLK_CCLK1_1_HALF 35 196 #define ADSP_SC58X_CLK_SHARC0_SEL 36 197 #define ADSP_SC58X_CLK_SHARC1_SEL 37 198 #define ADSP_SC58X_CLK_ARM_SEL 38 199 #define ADSP_SC58X_CLK_CDU_DDR_SEL 39 200 #define ADSP_SC58X_CLK_CAN_SEL 40 201 #define ADSP_SC58X_CLK_SPDIF_SEL 41 202 #define ADSP_SC58X_CLK_RESERVED_SEL 42 203 #define ADSP_SC58X_CLK_GIGE_SEL 43 204 #define ADSP_SC58X_CLK_LP_SEL 44 205 #define ADSP_SC58X_CLK_SDIO_SEL 45 206 #define ADSP_SC58X_CLK_SHARC0 46 207 #define ADSP_SC58X_CLK_SHARC1 47 208 #define ADSP_SC58X_CLK_ARM 48 209 #define ADSP_SC58X_CLK_CDU_DDR 49 210 #define ADSP_SC58X_CLK_CAN 50 211 #define ADSP_SC58X_CLK_SPDIF 51 212 #define ADSP_SC58X_CLK_RESERVED 52 213 #define ADSP_SC58X_CLK_GIGE 53 214 #define ADSP_SC58X_CLK_LP 54 215 #define ADSP_SC58X_CLK_SDIO 55 216 #define ADSP_SC58X_CLK_END 56 217 218 //ADSP-SC57X 219 #define ADSP_SC57X_CLK_DUMMY 0 220 #define ADSP_SC57X_CLK_SYS_CLKIN0 1 221 #define ADSP_SC57X_CLK_SYS_CLKIN1 2 222 #define ADSP_SC57X_CLK_CGU0_PLL_IN 3 223 #define ADSP_SC57X_CLK_CGU0_PLLCLK 4 224 #define ADSP_SC57X_CLK_CGU1_IN 5 225 #define ADSP_SC57X_CLK_CGU1_PLL_IN 6 226 #define ADSP_SC57X_CLK_CGU1_PLLCLK 7 227 #define ADSP_SC57X_CLK_CGU0_CDIV 8 228 #define ADSP_SC57X_CLK_CGU0_SYSCLK 9 229 #define ADSP_SC57X_CLK_CGU0_DDIV 10 230 #define ADSP_SC57X_CLK_CGU0_ODIV 11 231 #define ADSP_SC57X_CLK_CGU0_S0SELDIV 12 232 #define ADSP_SC57X_CLK_CGU0_S1SELDIV 13 233 #define ADSP_SC57X_CLK_CGU1_CDIV 14 234 #define ADSP_SC57X_CLK_CGU1_SYSCLK 15 235 #define ADSP_SC57X_CLK_CGU1_DDIV 16 236 #define ADSP_SC57X_CLK_CGU1_ODIV 17 237 #define ADSP_SC57X_CLK_CGU1_S0SELDIV 18 238 #define ADSP_SC57X_CLK_CGU1_S1SELDIV 19 239 #define ADSP_SC57X_CLK_CGU0_CCLK0 20 240 #define ADSP_SC57X_CLK_CGU0_CCLK1 21 241 #define ADSP_SC57X_CLK_CGU0_OCLK 22 242 #define ADSP_SC57X_CLK_CGU0_DCLK 23 243 #define ADSP_SC57X_CLK_CGU0_SCLK1 24 244 #define ADSP_SC57X_CLK_CGU0_SCLK0 25 245 #define ADSP_SC57X_CLK_CGU1_CCLK0 26 246 #define ADSP_SC57X_CLK_CGU1_CCLK1 27 247 #define ADSP_SC57X_CLK_CGU1_OCLK 28 248 #define ADSP_SC57X_CLK_CGU1_DCLK 29 249 #define ADSP_SC57X_CLK_CGU1_SCLK1 30 250 #define ADSP_SC57X_CLK_CGU1_SCLK0 31 251 #define ADSP_SC57X_CLK_OCLK0_HALF 32 252 #define ADSP_SC57X_CLK_CCLK1_1_HALF 33 253 #define ADSP_SC57X_CLK_SHARC0_SEL 34 254 #define ADSP_SC57X_CLK_SHARC1_SEL 35 255 #define ADSP_SC57X_CLK_ARM_SEL 36 256 #define ADSP_SC57X_CLK_CDU_DDR_SEL 37 257 #define ADSP_SC57X_CLK_CAN_SEL 38 258 #define ADSP_SC57X_CLK_SPDIF_SEL 39 259 #define ADSP_SC57X_CLK_GIGE_SEL 40 260 #define ADSP_SC57X_CLK_SDIO_SEL 41 261 #define ADSP_SC57X_CLK_SHARC0 42 262 #define ADSP_SC57X_CLK_SHARC1 43 263 #define ADSP_SC57X_CLK_ARM 44 264 #define ADSP_SC57X_CLK_CDU_DDR 45 265 #define ADSP_SC57X_CLK_CAN 46 266 #define ADSP_SC57X_CLK_SPDIF 47 267 #define ADSP_SC57X_CLK_GIGE 48 268 #define ADSP_SC57X_CLK_SDIO 49 269 #define ADSP_SC57X_CLK_END 50 270 271 #endif 272