1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2024 MediaTek Inc. 4 * Author: Lu Tang <Lu.Tang@mediatek.com> 5 * Author: Sam Shih <sam.shih@mediatek.com> 6 */ 7 8 #ifndef _DT_BINDINGS_CLK_MT7987_H 9 #define _DT_BINDINGS_CLK_MT7987_H 10 11 /* INFRACFG */ 12 13 #define CLK_INFRA_MUX_UART0_SEL 0 14 #define CLK_INFRA_MUX_UART1_SEL 1 15 #define CLK_INFRA_MUX_UART2_SEL 2 16 #define CLK_INFRA_MUX_SPI0_SEL 3 17 #define CLK_INFRA_MUX_SPI1_SEL 4 18 #define CLK_INFRA_MUX_SPI2_BCK_SEL 5 19 #define CLK_INFRA_PWM_BCK_SEL 6 20 #define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 7 21 #define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 8 22 #define CLK_INFRA_66M_GPT_BCK 9 23 #define CLK_INFRA_66M_PWM_HCK 10 24 #define CLK_INFRA_66M_PWM_BCK 11 25 #define CLK_INFRA_133M_CQDMA_BCK 12 26 #define CLK_INFRA_66M_AUD_SLV_BCK 13 27 #define CLK_INFRA_AUD_26M 14 28 #define CLK_INFRA_AUD_L 15 29 #define CLK_INFRA_AUD_AUD 16 30 #define CLK_INFRA_AUD_EG2 17 31 #define CLK_INFRA_DRAMC_F26M 18 32 #define CLK_INFRA_133M_DBG_ACKM 19 33 #define CLK_INFRA_66M_AP_DMA_BCK 20 34 #define CLK_INFRA_MSDC200_SRC 21 35 #define CLK_INFRA_66M_SEJ_BCK 22 36 #define CLK_INFRA_PRE_CK_SEJ_F13M 23 37 #define CLK_INFRA_66M_TRNG 24 38 #define CLK_INFRA_26M_THERM_SYSTEM 25 39 #define CLK_INFRA_I2C_BCK 26 40 #define CLK_INFRA_66M_UART0_PCK 27 41 #define CLK_INFRA_66M_UART1_PCK 28 42 #define CLK_INFRA_66M_UART2_PCK 29 43 #define CLK_INFRA_52M_UART0_CK 30 44 #define CLK_INFRA_52M_UART1_CK 31 45 #define CLK_INFRA_52M_UART2_CK 32 46 #define CLK_INFRA_NFI 33 47 #define CLK_INFRA_66M_NFI_HCK 34 48 #define CLK_INFRA_104M_SPI0 35 49 #define CLK_INFRA_104M_SPI1 36 50 #define CLK_INFRA_104M_SPI2_BCK 37 51 #define CLK_INFRA_66M_SPI0_HCK 38 52 #define CLK_INFRA_66M_SPI1_HCK 39 53 #define CLK_INFRA_66M_SPI2_HCK 40 54 #define CLK_INFRA_66M_FLASHIF_AXI 41 55 #define CLK_INFRA_RTC 42 56 #define CLK_INFRA_26M_ADC_BCK 43 57 #define CLK_INFRA_RC_ADC 44 58 #define CLK_INFRA_MSDC400 45 59 #define CLK_INFRA_MSDC2_HCK 46 60 #define CLK_INFRA_133M_MSDC_0_HCK 47 61 #define CLK_INFRA_66M_MSDC_0_HCK 48 62 #define CLK_INFRA_133M_CPUM_BCK 49 63 #define CLK_INFRA_BIST2FPC 50 64 #define CLK_INFRA_I2C_X16W_MCK_CK_P1 51 65 #define CLK_INFRA_I2C_X16W_PCK_CK_P1 52 66 #define CLK_INFRA_133M_USB_HCK 53 67 #define CLK_INFRA_133M_USB_HCK_CK_P1 54 68 #define CLK_INFRA_66M_USB_HCK 55 69 #define CLK_INFRA_66M_USB_HCK_CK_P1 56 70 #define CLK_INFRA_USB_SYS_CK_P1 57 71 #define CLK_INFRA_USB_CK_P1 58 72 #define CLK_INFRA_USB_FRMCNT_CK_P1 59 73 #define CLK_INFRA_USB_PIPE_CK_P1 60 74 #define CLK_INFRA_USB_UTMI_CK_P1 61 75 #define CLK_INFRA_USB_XHCI_CK_P1 62 76 #define CLK_INFRA_PCIE_GFMUX_TL_P0 63 77 #define CLK_INFRA_PCIE_GFMUX_TL_P1 64 78 #define CLK_INFRA_PCIE_PIPE_P0 65 79 #define CLK_INFRA_PCIE_PIPE_P1 66 80 #define CLK_INFRA_133M_PCIE_CK_P0 67 81 #define CLK_INFRA_133M_PCIE_CK_P1 68 82 #define CLK_INFRA_PCIE_PERI_26M_CK_P0 69 83 #define CLK_INFRA_PCIE_PERI_26M_CK_P1 70 84 #define CLK_INFRA_NR_CLK 71 85 86 /* TOPCKGEN */ 87 88 #define CLK_TOP_CB_M_D2 0 89 #define CLK_TOP_CB_M_D3 1 90 #define CLK_TOP_M_D3_D2 2 91 #define CLK_TOP_CB_M_D4 3 92 #define CLK_TOP_CB_M_D8 4 93 #define CLK_TOP_M_D8_D2 5 94 #define CLK_TOP_CB_APLL2_D4 6 95 #define CLK_TOP_CB_NET1_D3 7 96 #define CLK_TOP_CB_NET1_D4 8 97 #define CLK_TOP_CB_NET1_D5 9 98 #define CLK_TOP_NET1_D5_D2 10 99 #define CLK_TOP_NET1_D5_D4 11 100 #define CLK_TOP_CB_NET1_D7 12 101 #define CLK_TOP_NET1_D7_D2 13 102 #define CLK_TOP_NET1_D7_D4 14 103 #define CLK_TOP_NET1_D8_D2 15 104 #define CLK_TOP_NET1_D8_D4 16 105 #define CLK_TOP_NET1_D8_D8 17 106 #define CLK_TOP_NET1_D8_D16 18 107 #define CLK_TOP_CB_NET2_D2 19 108 #define CLK_TOP_CB_NET2_D4 20 109 #define CLK_TOP_NET2_D4_D4 21 110 #define CLK_TOP_NET2_D4_D8 22 111 #define CLK_TOP_CB_NET2_D6 23 112 #define CLK_TOP_NET2_D7_D2 24 113 #define CLK_TOP_CB_NET2_D8 25 114 #define CLK_TOP_MSDC_D2 26 115 #define CLK_TOP_CB_CKSQ_40M 27 116 #define CLK_TOP_CKSQ_40M_D2 28 117 #define CLK_TOP_CB_RTC_32K 29 118 #define CLK_TOP_CB_RTC_32P7K 30 119 #define CLK_TOP_NETSYS_SEL 31 120 #define CLK_TOP_NETSYS_500M_SEL 32 121 #define CLK_TOP_NETSYS_2X_SEL 33 122 #define CLK_TOP_ETH_GMII_SEL 34 123 #define CLK_TOP_EIP_SEL 35 124 #define CLK_TOP_AXI_INFRA_SEL 36 125 #define CLK_TOP_UART_SEL 37 126 #define CLK_TOP_EMMC_250M_SEL 38 127 #define CLK_TOP_EMMC_400M_SEL 39 128 #define CLK_TOP_SPI_SEL 40 129 #define CLK_TOP_SPIM_MST_SEL 41 130 #define CLK_TOP_NFI_SEL 42 131 #define CLK_TOP_PWM_SEL 43 132 #define CLK_TOP_I2C_SEL 44 133 #define CLK_TOP_PCIE_MBIST_250M_SEL 45 134 #define CLK_TOP_PEXTP_TL_SEL 46 135 #define CLK_TOP_PEXTP_TL_P1_SEL 47 136 #define CLK_TOP_USB_SYS_P1_SEL 48 137 #define CLK_TOP_USB_XHCI_P1_SEL 49 138 #define CLK_TOP_AUD_SEL 50 139 #define CLK_TOP_A1SYS_SEL 51 140 #define CLK_TOP_AUD_L_SEL 52 141 #define CLK_TOP_A_TUNER_SEL 53 142 #define CLK_TOP_USB_PHY_SEL 54 143 #define CLK_TOP_SGM_0_SEL 55 144 #define CLK_TOP_SGM_SBUS_0_SEL 56 145 #define CLK_TOP_SGM_1_SEL 57 146 #define CLK_TOP_SGM_SBUS_1_SEL 58 147 #define CLK_TOP_SYSAXI_SEL 59 148 #define CLK_TOP_SYSAPB_SEL 60 149 #define CLK_TOP_ETH_REFCK_50M_SEL 61 150 #define CLK_TOP_ETH_SYS_200M_SEL 62 151 #define CLK_TOP_ETH_SYS_SEL 63 152 #define CLK_TOP_ETH_XGMII_SEL 64 153 #define CLK_TOP_DRAMC_SEL 65 154 #define CLK_TOP_DRAMC_MD32_SEL 66 155 #define CLK_TOP_INFRA_F26M_SEL 67 156 #define CLK_TOP_PEXTP_P0_SEL 68 157 #define CLK_TOP_PEXTP_P1_SEL 69 158 #define CLK_TOP_DA_XTP_GLB_P0_SEL 70 159 #define CLK_TOP_DA_XTP_GLB_P1_SEL 71 160 #define CLK_TOP_CKM_SEL 72 161 #define CLK_TOP_DA_CKM_XTAL_SEL 73 162 #define CLK_TOP_PEXTP_SEL 74 163 #define CLK_TOP_ETH_MII_SEL 75 164 #define CLK_TOP_EMMC_200M_SEL 76 165 #define CLK_TOP_AUD_I2S_M 77 166 #define CLK_TOP_NR_CLK 78 167 168 /* APMIXEDSYS */ 169 170 #define CLK_APMIXED_MPLL 0 171 #define CLK_APMIXED_APLL2 1 172 #define CLK_APMIXED_NET1PLL 2 173 #define CLK_APMIXED_NET2PLL 3 174 #define CLK_APMIXED_WEDMCUPLL 4 175 #define CLK_APMIXED_SGMPLL 5 176 #define CLK_APMIXED_ARM_LL 6 177 #define CLK_APMIXED_MSDCPLL 7 178 #define CLK_APMIXED_NR_CLK 8 179 180 /* MCUSYS */ 181 182 #define CLK_MCU_BUS_DIV_SEL 0 183 #define CLK_MCU_NR_CLK 1 184 185 /* SGMIISYS_0 */ 186 187 #define CLK_SGM0_TX_EN 0 188 #define CLK_SGM0_RX_EN 1 189 #define CLK_SGMII0_NR_CLK 2 190 191 /* SGMIISYS_1 */ 192 193 #define CLK_SGM1_TX_EN 0 194 #define CLK_SGM1_RX_EN 1 195 #define CLK_SGMII1_NR_CLK 2 196 197 /* ETHDMA */ 198 199 #define CLK_ETHDMA_FE_EN 0 200 #define CLK_ETHDMA_GP2_EN 1 201 #define CLK_ETHDMA_GP1_EN 2 202 #define CLK_ETHDMA_GP3_EN 3 203 #define CLK_ETHDMA_NR_CLK 4 204 205 #endif /* _DT_BINDINGS_CLK_MT7987_H */ 206 207