1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 MediaTek Inc. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_MT2701_H 7 #define _DT_BINDINGS_CLK_MT2701_H 8 9 /* TOPCKGEN */ 10 #define CLK_TOP_SYSPLL 1 11 #define CLK_TOP_SYSPLL_D2 2 12 #define CLK_TOP_SYSPLL_D3 3 13 #define CLK_TOP_SYSPLL_D5 4 14 #define CLK_TOP_SYSPLL_D7 5 15 #define CLK_TOP_SYSPLL1_D2 6 16 #define CLK_TOP_SYSPLL1_D4 7 17 #define CLK_TOP_SYSPLL1_D8 8 18 #define CLK_TOP_SYSPLL1_D16 9 19 #define CLK_TOP_SYSPLL2_D2 10 20 #define CLK_TOP_SYSPLL2_D4 11 21 #define CLK_TOP_SYSPLL2_D8 12 22 #define CLK_TOP_SYSPLL3_D2 13 23 #define CLK_TOP_SYSPLL3_D4 14 24 #define CLK_TOP_SYSPLL4_D2 15 25 #define CLK_TOP_SYSPLL4_D4 16 26 #define CLK_TOP_UNIVPLL 17 27 #define CLK_TOP_UNIVPLL_D2 18 28 #define CLK_TOP_UNIVPLL_D3 19 29 #define CLK_TOP_UNIVPLL_D5 20 30 #define CLK_TOP_UNIVPLL_D7 21 31 #define CLK_TOP_UNIVPLL_D26 22 32 #define CLK_TOP_UNIVPLL_D52 23 33 #define CLK_TOP_UNIVPLL_D108 24 34 #define CLK_TOP_USB_PHY48M 25 35 #define CLK_TOP_UNIVPLL1_D2 26 36 #define CLK_TOP_UNIVPLL1_D4 27 37 #define CLK_TOP_UNIVPLL1_D8 28 38 #define CLK_TOP_UNIVPLL2_D2 29 39 #define CLK_TOP_UNIVPLL2_D4 30 40 #define CLK_TOP_UNIVPLL2_D8 31 41 #define CLK_TOP_UNIVPLL2_D16 32 42 #define CLK_TOP_UNIVPLL2_D32 33 43 #define CLK_TOP_UNIVPLL3_D2 34 44 #define CLK_TOP_UNIVPLL3_D4 35 45 #define CLK_TOP_UNIVPLL3_D8 36 46 #define CLK_TOP_MSDCPLL 37 47 #define CLK_TOP_MSDCPLL_D2 38 48 #define CLK_TOP_MSDCPLL_D4 39 49 #define CLK_TOP_MSDCPLL_D8 40 50 #define CLK_TOP_MMPLL 41 51 #define CLK_TOP_MMPLL_D2 42 52 #define CLK_TOP_DMPLL 43 53 #define CLK_TOP_DMPLL_D2 44 54 #define CLK_TOP_DMPLL_D4 45 55 #define CLK_TOP_DMPLL_X2 46 56 #define CLK_TOP_TVDPLL 47 57 #define CLK_TOP_TVDPLL_D2 48 58 #define CLK_TOP_TVDPLL_D4 49 59 #define CLK_TOP_TVD2PLL 50 60 #define CLK_TOP_TVD2PLL_D2 51 61 #define CLK_TOP_HADDS2PLL_98M 52 62 #define CLK_TOP_HADDS2PLL_294M 53 63 #define CLK_TOP_HADDS2_FB 54 64 #define CLK_TOP_MIPIPLL_D2 55 65 #define CLK_TOP_MIPIPLL_D4 56 66 #define CLK_TOP_HDMIPLL 57 67 #define CLK_TOP_HDMIPLL_D2 58 68 #define CLK_TOP_HDMIPLL_D3 59 69 #define CLK_TOP_HDMI_SCL_RX 60 70 #define CLK_TOP_HDMI_0_PIX340M 61 71 #define CLK_TOP_HDMI_0_DEEP340M 62 72 #define CLK_TOP_HDMI_0_PLL340M 63 73 #define CLK_TOP_AUD1PLL_98M 64 74 #define CLK_TOP_AUD2PLL_90M 65 75 #define CLK_TOP_AUDPLL 66 76 #define CLK_TOP_AUDPLL_D4 67 77 #define CLK_TOP_AUDPLL_D8 68 78 #define CLK_TOP_AUDPLL_D16 69 79 #define CLK_TOP_AUDPLL_D24 70 80 #define CLK_TOP_ETHPLL_500M 71 81 #define CLK_TOP_VDECPLL 72 82 #define CLK_TOP_VENCPLL 73 83 #define CLK_TOP_MIPIPLL 74 84 #define CLK_TOP_ARMPLL_1P3G 75 85 86 #define CLK_TOP_MM_SEL 76 87 #define CLK_TOP_DDRPHYCFG_SEL 77 88 #define CLK_TOP_MEM_SEL 78 89 #define CLK_TOP_AXI_SEL 79 90 #define CLK_TOP_CAMTG_SEL 80 91 #define CLK_TOP_MFG_SEL 81 92 #define CLK_TOP_VDEC_SEL 82 93 #define CLK_TOP_PWM_SEL 83 94 #define CLK_TOP_MSDC30_0_SEL 84 95 #define CLK_TOP_USB20_SEL 85 96 #define CLK_TOP_SPI0_SEL 86 97 #define CLK_TOP_UART_SEL 87 98 #define CLK_TOP_AUDINTBUS_SEL 88 99 #define CLK_TOP_AUDIO_SEL 89 100 #define CLK_TOP_MSDC30_2_SEL 90 101 #define CLK_TOP_MSDC30_1_SEL 91 102 #define CLK_TOP_DPI1_SEL 92 103 #define CLK_TOP_DPI0_SEL 93 104 #define CLK_TOP_SCP_SEL 94 105 #define CLK_TOP_PMICSPI_SEL 95 106 #define CLK_TOP_APLL_SEL 96 107 #define CLK_TOP_HDMI_SEL 97 108 #define CLK_TOP_TVE_SEL 98 109 #define CLK_TOP_EMMC_HCLK_SEL 99 110 #define CLK_TOP_NFI2X_SEL 100 111 #define CLK_TOP_RTC_SEL 101 112 #define CLK_TOP_OSD_SEL 102 113 #define CLK_TOP_NR_SEL 103 114 #define CLK_TOP_DI_SEL 104 115 #define CLK_TOP_FLASH_SEL 105 116 #define CLK_TOP_ASM_M_SEL 106 117 #define CLK_TOP_ASM_I_SEL 107 118 #define CLK_TOP_INTDIR_SEL 108 119 #define CLK_TOP_HDMIRX_BIST_SEL 109 120 #define CLK_TOP_ETHIF_SEL 110 121 #define CLK_TOP_MS_CARD_SEL 111 122 #define CLK_TOP_ASM_H_SEL 112 123 #define CLK_TOP_SPI1_SEL 113 124 #define CLK_TOP_CMSYS_SEL 114 125 #define CLK_TOP_MSDC30_3_SEL 115 126 #define CLK_TOP_HDMIRX26_24_SEL 116 127 #define CLK_TOP_AUD2DVD_SEL 117 128 #define CLK_TOP_8BDAC_SEL 118 129 #define CLK_TOP_SPI2_SEL 119 130 #define CLK_TOP_AUD_MUX1_SEL 120 131 #define CLK_TOP_AUD_MUX2_SEL 121 132 #define CLK_TOP_AUDPLL_MUX_SEL 122 133 #define CLK_TOP_AUD_K1_SRC_SEL 123 134 #define CLK_TOP_AUD_K2_SRC_SEL 124 135 #define CLK_TOP_AUD_K3_SRC_SEL 125 136 #define CLK_TOP_AUD_K4_SRC_SEL 126 137 #define CLK_TOP_AUD_K5_SRC_SEL 127 138 #define CLK_TOP_AUD_K6_SRC_SEL 128 139 #define CLK_TOP_PADMCLK_SEL 129 140 #define CLK_TOP_AUD_EXTCK1_DIV 130 141 #define CLK_TOP_AUD_EXTCK2_DIV 131 142 #define CLK_TOP_AUD_MUX1_DIV 132 143 #define CLK_TOP_AUD_MUX2_DIV 133 144 #define CLK_TOP_AUD_K1_SRC_DIV 134 145 #define CLK_TOP_AUD_K2_SRC_DIV 135 146 #define CLK_TOP_AUD_K3_SRC_DIV 136 147 #define CLK_TOP_AUD_K4_SRC_DIV 137 148 #define CLK_TOP_AUD_K5_SRC_DIV 138 149 #define CLK_TOP_AUD_K6_SRC_DIV 139 150 #define CLK_TOP_AUD_I2S1_MCLK 140 151 #define CLK_TOP_AUD_I2S2_MCLK 141 152 #define CLK_TOP_AUD_I2S3_MCLK 142 153 #define CLK_TOP_AUD_I2S4_MCLK 143 154 #define CLK_TOP_AUD_I2S5_MCLK 144 155 #define CLK_TOP_AUD_I2S6_MCLK 145 156 #define CLK_TOP_AUD_48K_TIMING 146 157 #define CLK_TOP_AUD_44K_TIMING 147 158 159 #define CLK_TOP_32K_INTERNAL 148 160 #define CLK_TOP_32K_EXTERNAL 149 161 #define CLK_TOP_CLK26M_D8 150 162 #define CLK_TOP_8BDAC 151 163 #define CLK_TOP_WBG_DIG_416M 152 164 #define CLK_TOP_DPI 153 165 #define CLK_TOP_DSI0_LNTC_DSI 154 166 #define CLK_TOP_AUD_EXT1 155 167 #define CLK_TOP_AUD_EXT2 156 168 #define CLK_TOP_NFI1X_PAD 157 169 #define CLK_TOP_AXISEL_D4 158 170 #define CLK_TOP_NR 159 171 172 /* APMIXEDSYS */ 173 174 #define CLK_APMIXED_ARMPLL 1 175 #define CLK_APMIXED_MAINPLL 2 176 #define CLK_APMIXED_UNIVPLL 3 177 #define CLK_APMIXED_MMPLL 4 178 #define CLK_APMIXED_MSDCPLL 5 179 #define CLK_APMIXED_TVDPLL 6 180 #define CLK_APMIXED_AUD1PLL 7 181 #define CLK_APMIXED_TRGPLL 8 182 #define CLK_APMIXED_ETHPLL 9 183 #define CLK_APMIXED_VDECPLL 10 184 #define CLK_APMIXED_HADDS2PLL 11 185 #define CLK_APMIXED_AUD2PLL 12 186 #define CLK_APMIXED_TVD2PLL 13 187 #define CLK_APMIXED_HDMI_REF 14 188 #define CLK_APMIXED_NR 15 189 190 /* DDRPHY */ 191 192 #define CLK_DDRPHY_VENCPLL 1 193 #define CLK_DDRPHY_NR 2 194 195 /* INFRACFG */ 196 197 #define CLK_INFRA_DBG 1 198 #define CLK_INFRA_SMI 2 199 #define CLK_INFRA_QAXI_CM4 3 200 #define CLK_INFRA_AUD_SPLIN_B 4 201 #define CLK_INFRA_AUDIO 5 202 #define CLK_INFRA_EFUSE 6 203 #define CLK_INFRA_L2C_SRAM 7 204 #define CLK_INFRA_M4U 8 205 #define CLK_INFRA_CONNMCU 9 206 #define CLK_INFRA_TRNG 10 207 #define CLK_INFRA_RAMBUFIF 11 208 #define CLK_INFRA_CPUM 12 209 #define CLK_INFRA_KP 13 210 #define CLK_INFRA_CEC 14 211 #define CLK_INFRA_IRRX 15 212 #define CLK_INFRA_PMICSPI 16 213 #define CLK_INFRA_PMICWRAP 17 214 #define CLK_INFRA_DDCCI 18 215 #define CLK_INFRA_CLK_13M 19 216 #define CLK_INFRA_CPUSEL 20 217 #define CLK_INFRA_NR 21 218 219 /* PERICFG */ 220 221 #define CLK_PERI_NFI 1 222 #define CLK_PERI_THERM 2 223 #define CLK_PERI_PWM1 3 224 #define CLK_PERI_PWM2 4 225 #define CLK_PERI_PWM3 5 226 #define CLK_PERI_PWM4 6 227 #define CLK_PERI_PWM5 7 228 #define CLK_PERI_PWM6 8 229 #define CLK_PERI_PWM7 9 230 #define CLK_PERI_PWM 10 231 #define CLK_PERI_USB0 11 232 #define CLK_PERI_USB1 12 233 #define CLK_PERI_AP_DMA 13 234 #define CLK_PERI_MSDC30_0 14 235 #define CLK_PERI_MSDC30_1 15 236 #define CLK_PERI_MSDC30_2 16 237 #define CLK_PERI_MSDC30_3 17 238 #define CLK_PERI_MSDC50_3 18 239 #define CLK_PERI_NLI 19 240 #define CLK_PERI_UART0 20 241 #define CLK_PERI_UART1 21 242 #define CLK_PERI_UART2 22 243 #define CLK_PERI_UART3 23 244 #define CLK_PERI_BTIF 24 245 #define CLK_PERI_I2C0 25 246 #define CLK_PERI_I2C1 26 247 #define CLK_PERI_I2C2 27 248 #define CLK_PERI_I2C3 28 249 #define CLK_PERI_AUXADC 29 250 #define CLK_PERI_SPI0 30 251 #define CLK_PERI_ETH 31 252 #define CLK_PERI_USB0_MCU 32 253 254 #define CLK_PERI_USB1_MCU 33 255 #define CLK_PERI_USB_SLV 34 256 #define CLK_PERI_GCPU 35 257 #define CLK_PERI_NFI_ECC 36 258 #define CLK_PERI_NFI_PAD 37 259 #define CLK_PERI_FLASH 38 260 #define CLK_PERI_HOST89_INT 39 261 #define CLK_PERI_HOST89_SPI 40 262 #define CLK_PERI_HOST89_DVD 41 263 #define CLK_PERI_SPI1 42 264 #define CLK_PERI_SPI2 43 265 #define CLK_PERI_FCI 44 266 267 #define CLK_PERI_UART0_SEL 45 268 #define CLK_PERI_UART1_SEL 46 269 #define CLK_PERI_UART2_SEL 47 270 #define CLK_PERI_UART3_SEL 48 271 #define CLK_PERI_NR 49 272 273 /* AUDIO */ 274 275 #define CLK_AUD_AFE 1 276 #define CLK_AUD_LRCK_DETECT 2 277 #define CLK_AUD_I2S 3 278 #define CLK_AUD_APLL_TUNER 4 279 #define CLK_AUD_HDMI 5 280 #define CLK_AUD_SPDF 6 281 #define CLK_AUD_SPDF2 7 282 #define CLK_AUD_APLL 8 283 #define CLK_AUD_TML 9 284 #define CLK_AUD_AHB_IDLE_EXT 10 285 #define CLK_AUD_AHB_IDLE_INT 11 286 287 #define CLK_AUD_I2SIN1 12 288 #define CLK_AUD_I2SIN2 13 289 #define CLK_AUD_I2SIN3 14 290 #define CLK_AUD_I2SIN4 15 291 #define CLK_AUD_I2SIN5 16 292 #define CLK_AUD_I2SIN6 17 293 #define CLK_AUD_I2SO1 18 294 #define CLK_AUD_I2SO2 19 295 #define CLK_AUD_I2SO3 20 296 #define CLK_AUD_I2SO4 21 297 #define CLK_AUD_I2SO5 22 298 #define CLK_AUD_I2SO6 23 299 #define CLK_AUD_ASRCI1 24 300 #define CLK_AUD_ASRCI2 25 301 #define CLK_AUD_ASRCO1 26 302 #define CLK_AUD_ASRCO2 27 303 #define CLK_AUD_ASRC11 28 304 #define CLK_AUD_ASRC12 29 305 #define CLK_AUD_HDMIRX 30 306 #define CLK_AUD_INTDIR 31 307 #define CLK_AUD_A1SYS 32 308 #define CLK_AUD_A2SYS 33 309 #define CLK_AUD_AFE_CONN 34 310 #define CLK_AUD_AFE_PCMIF 35 311 #define CLK_AUD_AFE_MRGIF 36 312 313 #define CLK_AUD_MMIF_UL1 37 314 #define CLK_AUD_MMIF_UL2 38 315 #define CLK_AUD_MMIF_UL3 39 316 #define CLK_AUD_MMIF_UL4 40 317 #define CLK_AUD_MMIF_UL5 41 318 #define CLK_AUD_MMIF_UL6 42 319 #define CLK_AUD_MMIF_DL1 43 320 #define CLK_AUD_MMIF_DL2 44 321 #define CLK_AUD_MMIF_DL3 45 322 #define CLK_AUD_MMIF_DL4 46 323 #define CLK_AUD_MMIF_DL5 47 324 #define CLK_AUD_MMIF_DL6 48 325 #define CLK_AUD_MMIF_DLMCH 49 326 #define CLK_AUD_MMIF_ARB1 50 327 #define CLK_AUD_MMIF_AWB1 51 328 #define CLK_AUD_MMIF_AWB2 52 329 #define CLK_AUD_MMIF_DAI 53 330 331 #define CLK_AUD_DMIC1 54 332 #define CLK_AUD_DMIC2 55 333 #define CLK_AUD_ASRCI3 56 334 #define CLK_AUD_ASRCI4 57 335 #define CLK_AUD_ASRCI5 58 336 #define CLK_AUD_ASRCI6 59 337 #define CLK_AUD_ASRCO3 60 338 #define CLK_AUD_ASRCO4 61 339 #define CLK_AUD_ASRCO5 62 340 #define CLK_AUD_ASRCO6 63 341 #define CLK_AUD_MEM_ASRC1 64 342 #define CLK_AUD_MEM_ASRC2 65 343 #define CLK_AUD_MEM_ASRC3 66 344 #define CLK_AUD_MEM_ASRC4 67 345 #define CLK_AUD_MEM_ASRC5 68 346 #define CLK_AUD_DSD_ENC 69 347 #define CLK_AUD_ASRC_BRG 70 348 #define CLK_AUD_NR 71 349 350 /* MMSYS */ 351 352 #define CLK_MM_SMI_COMMON 1 353 #define CLK_MM_SMI_LARB0 2 354 #define CLK_MM_CMDQ 3 355 #define CLK_MM_MUTEX 4 356 #define CLK_MM_DISP_COLOR 5 357 #define CLK_MM_DISP_BLS 6 358 #define CLK_MM_DISP_WDMA 7 359 #define CLK_MM_DISP_RDMA 8 360 #define CLK_MM_DISP_OVL 9 361 #define CLK_MM_MDP_TDSHP 10 362 #define CLK_MM_MDP_WROT 11 363 #define CLK_MM_MDP_WDMA 12 364 #define CLK_MM_MDP_RSZ1 13 365 #define CLK_MM_MDP_RSZ0 14 366 #define CLK_MM_MDP_RDMA 15 367 #define CLK_MM_MDP_BLS_26M 16 368 #define CLK_MM_CAM_MDP 17 369 #define CLK_MM_FAKE_ENG 18 370 #define CLK_MM_MUTEX_32K 19 371 #define CLK_MM_DISP_RDMA1 20 372 #define CLK_MM_DISP_UFOE 21 373 374 #define CLK_MM_DSI_ENGINE 22 375 #define CLK_MM_DSI_DIG 23 376 #define CLK_MM_DPI_DIGL 24 377 #define CLK_MM_DPI_ENGINE 25 378 #define CLK_MM_DPI1_DIGL 26 379 #define CLK_MM_DPI1_ENGINE 27 380 #define CLK_MM_TVE_OUTPUT 28 381 #define CLK_MM_TVE_INPUT 29 382 #define CLK_MM_HDMI_PIXEL 30 383 #define CLK_MM_HDMI_PLL 31 384 #define CLK_MM_HDMI_AUDIO 32 385 #define CLK_MM_HDMI_SPDIF 33 386 #define CLK_MM_TVE_FMM 34 387 #define CLK_MM_NR 35 388 389 /* IMGSYS */ 390 391 #define CLK_IMG_SMI_COMM 1 392 #define CLK_IMG_RESZ 2 393 #define CLK_IMG_JPGDEC_SMI 3 394 #define CLK_IMG_JPGDEC 4 395 #define CLK_IMG_VENC_LT 5 396 #define CLK_IMG_VENC 6 397 #define CLK_IMG_NR 7 398 399 /* VDEC */ 400 401 #define CLK_VDEC_CKGEN 1 402 #define CLK_VDEC_LARB 2 403 #define CLK_VDEC_NR 3 404 405 /* HIFSYS */ 406 407 #define CLK_HIFSYS_USB0PHY 1 408 #define CLK_HIFSYS_USB1PHY 2 409 #define CLK_HIFSYS_PCIE0 3 410 #define CLK_HIFSYS_PCIE1 4 411 #define CLK_HIFSYS_PCIE2 5 412 #define CLK_HIFSYS_NR 6 413 414 /* ETHSYS */ 415 #define CLK_ETHSYS_HSDMA 1 416 #define CLK_ETHSYS_ESW 2 417 #define CLK_ETHSYS_GP2 3 418 #define CLK_ETHSYS_GP1 4 419 #define CLK_ETHSYS_PCM 5 420 #define CLK_ETHSYS_GDMA 6 421 #define CLK_ETHSYS_I2S 7 422 #define CLK_ETHSYS_CRYPTO 8 423 #define CLK_ETHSYS_NR 9 424 425 /* G3DSYS */ 426 #define CLK_G3DSYS_CORE 1 427 #define CLK_G3DSYS_NR 2 428 429 /* BDP */ 430 431 #define CLK_BDP_BRG_BA 1 432 #define CLK_BDP_BRG_DRAM 2 433 #define CLK_BDP_LARB_DRAM 3 434 #define CLK_BDP_WR_VDI_PXL 4 435 #define CLK_BDP_WR_VDI_DRAM 5 436 #define CLK_BDP_WR_B 6 437 #define CLK_BDP_DGI_IN 7 438 #define CLK_BDP_DGI_OUT 8 439 #define CLK_BDP_FMT_MAST_27 9 440 #define CLK_BDP_FMT_B 10 441 #define CLK_BDP_OSD_B 11 442 #define CLK_BDP_OSD_DRAM 12 443 #define CLK_BDP_OSD_AGENT 13 444 #define CLK_BDP_OSD_PXL 14 445 #define CLK_BDP_RLE_B 15 446 #define CLK_BDP_RLE_AGENT 16 447 #define CLK_BDP_RLE_DRAM 17 448 #define CLK_BDP_F27M 18 449 #define CLK_BDP_F27M_VDOUT 19 450 #define CLK_BDP_F27_74_74 20 451 #define CLK_BDP_F2FS 21 452 #define CLK_BDP_F2FS74_148 22 453 #define CLK_BDP_FB 23 454 #define CLK_BDP_VDO_DRAM 24 455 #define CLK_BDP_VDO_2FS 25 456 #define CLK_BDP_VDO_B 26 457 #define CLK_BDP_WR_DI_PXL 27 458 #define CLK_BDP_WR_DI_DRAM 28 459 #define CLK_BDP_WR_DI_B 29 460 #define CLK_BDP_NR_PXL 30 461 #define CLK_BDP_NR_DRAM 31 462 #define CLK_BDP_NR_B 32 463 464 #define CLK_BDP_RX_F 33 465 #define CLK_BDP_RX_X 34 466 #define CLK_BDP_RXPDT 35 467 #define CLK_BDP_RX_CSCL_N 36 468 #define CLK_BDP_RX_CSCL 37 469 #define CLK_BDP_RX_DDCSCL_N 38 470 #define CLK_BDP_RX_DDCSCL 39 471 #define CLK_BDP_RX_VCO 40 472 #define CLK_BDP_RX_DP 41 473 #define CLK_BDP_RX_P 42 474 #define CLK_BDP_RX_M 43 475 #define CLK_BDP_RX_PLL 44 476 #define CLK_BDP_BRG_RT_B 45 477 #define CLK_BDP_BRG_RT_DRAM 46 478 #define CLK_BDP_LARBRT_DRAM 47 479 #define CLK_BDP_TMDS_SYN 48 480 #define CLK_BDP_HDMI_MON 49 481 #define CLK_BDP_NR 50 482 483 #endif /* _DT_BINDINGS_CLK_MT2701_H */ 484