1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. All rights reserved. 4 * 5 * Author: Sam Shih <sam.shih@mediatek.com> 6 */ 7 8 #ifndef _DT_BINDINGS_CLK_MT7988_H 9 #define _DT_BINDINGS_CLK_MT7988_H 10 11 /* INFRACFG_AO */ 12 /* mtk_mux */ 13 #define CLK_INFRA_MUX_UART0_SEL 0 14 #define CLK_INFRA_MUX_UART1_SEL 1 15 #define CLK_INFRA_MUX_UART2_SEL 2 16 #define CLK_INFRA_MUX_SPI0_SEL 3 17 #define CLK_INFRA_MUX_SPI1_SEL 4 18 #define CLK_INFRA_MUX_SPI2_SEL 5 19 #define CLK_INFRA_PWM_SEL 6 20 #define CLK_INFRA_PWM_CK1_SEL 7 21 #define CLK_INFRA_PWM_CK2_SEL 8 22 #define CLK_INFRA_PWM_CK3_SEL 9 23 #define CLK_INFRA_PWM_CK4_SEL 10 24 #define CLK_INFRA_PWM_CK5_SEL 11 25 #define CLK_INFRA_PWM_CK6_SEL 12 26 #define CLK_INFRA_PWM_CK7_SEL 13 27 #define CLK_INFRA_PWM_CK8_SEL 14 28 #define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 29 #define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 30 #define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 31 #define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 32 33 /* INFRACFG */ 34 /* mtk_gate */ 35 #define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 36 #define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 37 #define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 38 #define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 39 #define CLK_INFRA_66M_GPT_BCK 23 40 #define CLK_INFRA_66M_PWM_HCK 24 41 #define CLK_INFRA_66M_PWM_BCK 25 42 #define CLK_INFRA_66M_PWM_CK1 26 43 #define CLK_INFRA_66M_PWM_CK2 27 44 #define CLK_INFRA_66M_PWM_CK3 28 45 #define CLK_INFRA_66M_PWM_CK4 29 46 #define CLK_INFRA_66M_PWM_CK5 30 47 #define CLK_INFRA_66M_PWM_CK6 31 48 #define CLK_INFRA_66M_PWM_CK7 32 49 #define CLK_INFRA_66M_PWM_CK8 33 50 #define CLK_INFRA_133M_CQDMA_BCK 34 51 #define CLK_INFRA_66M_AUD_SLV_BCK 35 52 #define CLK_INFRA_AUD_26M 36 53 #define CLK_INFRA_AUD_L 37 54 #define CLK_INFRA_AUD_AUD 38 55 #define CLK_INFRA_AUD_EG2 39 56 #define CLK_INFRA_DRAMC_F26M 40 57 #define CLK_INFRA_133M_DBG_ACKM 41 58 #define CLK_INFRA_66M_AP_DMA_BCK 42 59 #define CLK_INFRA_66M_SEJ_BCK 43 60 #define CLK_INFRA_PRE_CK_SEJ_F13M 44 61 /* #define CLK_INFRA_66M_TRNG 44 */ 62 #define CLK_INFRA_26M_THERM_SYSTEM 45 63 #define CLK_INFRA_I2C_BCK 46 64 /* #define CLK_INFRA_66M_UART0_PCK 46 */ 65 /* #define CLK_INFRA_66M_UART1_PCK 47 */ 66 /* #define CLK_INFRA_66M_UART2_PCK 48 */ 67 #define CLK_INFRA_52M_UART0_CK 47 68 #define CLK_INFRA_52M_UART1_CK 48 69 #define CLK_INFRA_52M_UART2_CK 49 70 #define CLK_INFRA_NFI 50 71 #define CLK_INFRA_SPINFI 51 72 #define CLK_INFRA_66M_NFI_HCK 52 73 #define CLK_INFRA_104M_SPI0 53 74 #define CLK_INFRA_104M_SPI1 54 75 #define CLK_INFRA_104M_SPI2_BCK 55 76 #define CLK_INFRA_66M_SPI0_HCK 56 77 #define CLK_INFRA_66M_SPI1_HCK 57 78 #define CLK_INFRA_66M_SPI2_HCK 58 79 #define CLK_INFRA_66M_FLASHIF_AXI 59 80 #define CLK_INFRA_RTC 60 81 #define CLK_INFRA_26M_ADC_BCK 61 82 #define CLK_INFRA_RC_ADC 62 83 #define CLK_INFRA_MSDC400 63 84 #define CLK_INFRA_MSDC2_HCK 64 85 #define CLK_INFRA_133M_MSDC_0_HCK 65 86 #define CLK_INFRA_66M_MSDC_0_HCK 66 87 #define CLK_INFRA_133M_CPUM_BCK 67 88 #define CLK_INFRA_BIST2FPC 68 89 #define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 90 #define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 91 #define CLK_INFRA_133M_USB_HCK 71 92 #define CLK_INFRA_133M_USB_HCK_CK_P1 72 93 #define CLK_INFRA_66M_USB_HCK 73 94 #define CLK_INFRA_66M_USB_HCK_CK_P1 74 95 #define CLK_INFRA_USB_SYS 75 96 #define CLK_INFRA_USB_SYS_CK_P1 76 97 #define CLK_INFRA_USB_REF 77 98 #define CLK_INFRA_USB_CK_P1 78 99 #define CLK_INFRA_USB_FRMCNT 79 100 #define CLK_INFRA_USB_FRMCNT_CK_P1 80 101 #define CLK_INFRA_USB_PIPE 81 102 #define CLK_INFRA_USB_PIPE_CK_P1 82 103 #define CLK_INFRA_USB_UTMI 83 104 #define CLK_INFRA_USB_UTMI_CK_P1 84 105 #define CLK_INFRA_USB_XHCI 85 106 #define CLK_INFRA_USB_XHCI_CK_P1 86 107 #define CLK_INFRA_PCIE_GFMUX_TL_P0 87 108 #define CLK_INFRA_PCIE_GFMUX_TL_P1 88 109 #define CLK_INFRA_PCIE_GFMUX_TL_P2 89 110 #define CLK_INFRA_PCIE_GFMUX_TL_P3 90 111 #define CLK_INFRA_PCIE_PIPE_P0 91 112 #define CLK_INFRA_PCIE_PIPE_P1 92 113 #define CLK_INFRA_PCIE_PIPE_P2 93 114 #define CLK_INFRA_PCIE_PIPE_P3 94 115 #define CLK_INFRA_133M_PCIE_CK_P0 95 116 #define CLK_INFRA_133M_PCIE_CK_P1 96 117 #define CLK_INFRA_133M_PCIE_CK_P2 97 118 #define CLK_INFRA_133M_PCIE_CK_P3 98 119 120 /* TOPCKGEN */ 121 /* mtk_fixed_clk */ 122 #define CLK_TOP_XTAL 0 123 /* mtk_fixed_factor */ 124 #define CLK_TOP_XTAL_D2 1 125 #define CLK_TOP_RTC_32K 2 126 #define CLK_TOP_RTC_32P7K 3 127 #define CLK_TOP_MPLL_D2 4 128 #define CLK_TOP_MPLL_D3_D2 5 129 #define CLK_TOP_MPLL_D4 6 130 #define CLK_TOP_MPLL_D8 7 131 #define CLK_TOP_MPLL_D8_D2 8 132 #define CLK_TOP_MMPLL_D2 9 133 #define CLK_TOP_MMPLL_D3_D5 10 134 #define CLK_TOP_MMPLL_D4 11 135 #define CLK_TOP_MMPLL_D6_D2 12 136 #define CLK_TOP_MMPLL_D8 13 137 #define CLK_TOP_APLL2_D4 14 138 #define CLK_TOP_NET1PLL_D4 15 139 #define CLK_TOP_NET1PLL_D5 16 140 #define CLK_TOP_NET1PLL_D5_D2 17 141 #define CLK_TOP_NET1PLL_D5_D4 18 142 #define CLK_TOP_NET1PLL_D8 19 143 #define CLK_TOP_NET1PLL_D8_D2 20 144 #define CLK_TOP_NET1PLL_D8_D4 21 145 #define CLK_TOP_NET1PLL_D8_D8 22 146 #define CLK_TOP_NET1PLL_D8_D16 23 147 #define CLK_TOP_NET2PLL_D2 24 148 #define CLK_TOP_NET2PLL_D4 25 149 #define CLK_TOP_NET2PLL_D4_D4 26 150 #define CLK_TOP_NET2PLL_D4_D8 27 151 #define CLK_TOP_NET2PLL_D6 28 152 #define CLK_TOP_NET2PLL_D8 29 153 /* mtk_mux */ 154 #define CLK_TOP_NETSYS_SEL 30 155 #define CLK_TOP_NETSYS_500M_SEL 31 156 #define CLK_TOP_NETSYS_2X_SEL 32 157 #define CLK_TOP_NETSYS_GSW_SEL 33 158 #define CLK_TOP_ETH_GMII_SEL 34 159 #define CLK_TOP_NETSYS_MCU_SEL 35 160 #define CLK_TOP_NETSYS_PAO_2X_SEL 36 161 #define CLK_TOP_EIP197_SEL 37 162 #define CLK_TOP_AXI_INFRA_SEL 38 163 #define CLK_TOP_UART_SEL 39 164 #define CLK_TOP_EMMC_250M_SEL 40 165 #define CLK_TOP_EMMC_400M_SEL 41 166 #define CLK_TOP_SPI_SEL 42 167 #define CLK_TOP_SPIM_MST_SEL 43 168 #define CLK_TOP_NFI1X_SEL 44 169 #define CLK_TOP_SPINFI_SEL 45 170 #define CLK_TOP_PWM_SEL 46 171 #define CLK_TOP_I2C_SEL 47 172 #define CLK_TOP_PCIE_MBIST_250M_SEL 48 173 #define CLK_TOP_PEXTP_TL_SEL 49 174 #define CLK_TOP_PEXTP_TL_P1_SEL 50 175 #define CLK_TOP_PEXTP_TL_P2_SEL 51 176 #define CLK_TOP_PEXTP_TL_P3_SEL 52 177 #define CLK_TOP_USB_SYS_SEL 53 178 #define CLK_TOP_USB_SYS_P1_SEL 54 179 #define CLK_TOP_USB_XHCI_SEL 55 180 #define CLK_TOP_USB_XHCI_P1_SEL 56 181 #define CLK_TOP_USB_FRMCNT_SEL 57 182 #define CLK_TOP_USB_FRMCNT_P1_SEL 58 183 #define CLK_TOP_AUD_SEL 59 184 #define CLK_TOP_A1SYS_SEL 60 185 #define CLK_TOP_AUD_L_SEL 61 186 #define CLK_TOP_A_TUNER_SEL 62 187 #define CLK_TOP_SSPXTP_SEL 63 188 #define CLK_TOP_USB_PHY_SEL 64 189 #define CLK_TOP_USXGMII_SBUS_0_SEL 65 190 #define CLK_TOP_USXGMII_SBUS_1_SEL 66 191 #define CLK_TOP_SGM_0_SEL 67 192 #define CLK_TOP_SGM_SBUS_0_SEL 68 193 #define CLK_TOP_SGM_1_SEL 69 194 #define CLK_TOP_SGM_SBUS_1_SEL 70 195 #define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 196 #define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 197 #define CLK_TOP_SYSAXI_SEL 73 198 #define CLK_TOP_SYSAPB_SEL 74 199 #define CLK_TOP_ETH_REFCK_50M_SEL 75 200 #define CLK_TOP_ETH_SYS_200M_SEL 76 201 #define CLK_TOP_ETH_SYS_SEL 77 202 #define CLK_TOP_ETH_XGMII_SEL 78 203 #define CLK_TOP_BUS_TOPS_SEL 79 204 #define CLK_TOP_NPU_TOPS_SEL 80 205 #define CLK_TOP_DRAMC_SEL 81 206 #define CLK_TOP_DRAMC_MD32_SEL 82 207 #define CLK_TOP_INFRA_F26M_SEL 83 208 #define CLK_TOP_PEXTP_P0_SEL 84 209 #define CLK_TOP_PEXTP_P1_SEL 85 210 #define CLK_TOP_PEXTP_P2_SEL 86 211 #define CLK_TOP_PEXTP_P3_SEL 87 212 #define CLK_TOP_DA_XTP_GLB_P0_SEL 88 213 #define CLK_TOP_DA_XTP_GLB_P1_SEL 89 214 #define CLK_TOP_DA_XTP_GLB_P2_SEL 90 215 #define CLK_TOP_DA_XTP_GLB_P3_SEL 91 216 #define CLK_TOP_CKM_SEL 92 217 #define CLK_TOP_DA_SEL 93 218 #define CLK_TOP_PEXTP_SEL 94 219 #define CLK_TOP_TOPS_P2_26M_SEL 95 220 #define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 221 #define CLK_TOP_NETSYS_SYNC_250M_SEL 97 222 #define CLK_TOP_MACSEC_SEL 98 223 #define CLK_TOP_NETSYS_TOPS_400M_SEL 99 224 #define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 225 #define CLK_TOP_NETSYS_WARP_SEL 101 226 #define CLK_TOP_ETH_MII_SEL 102 227 #define CLK_TOP_NPU_SEL 103 228 229 /* APMIXEDSYS */ 230 /* mtk_pll_data */ 231 #define CLK_APMIXED_NETSYSPLL 0 232 #define CLK_APMIXED_MPLL 1 233 #define CLK_APMIXED_MMPLL 2 234 #define CLK_APMIXED_APLL2 3 235 #define CLK_APMIXED_NET1PLL 4 236 #define CLK_APMIXED_NET2PLL 5 237 #define CLK_APMIXED_WEDMCUPLL 6 238 #define CLK_APMIXED_SGMPLL 7 239 #define CLK_APMIXED_ARM_B 8 240 #define CLK_APMIXED_CCIPLL2_B 9 241 #define CLK_APMIXED_USXGMIIPLL 10 242 #define CLK_APMIXED_MSDCPLL 11 243 244 /* ETHSYS ETH DMA */ 245 /* mtk_gate */ 246 #define CLK_ETHDMA_FE_EN 0 247 248 /* SGMIISYS_0 */ 249 /* mtk_gate */ 250 #define CLK_SGM0_TX_EN 0 251 #define CLK_SGM0_RX_EN 1 252 253 /* SGMIISYS_1 */ 254 /* mtk_gate */ 255 #define CLK_SGM1_TX_EN 0 256 #define CLK_SGM1_RX_EN 1 257 258 /* ETHWARP */ 259 /* mtk_gate */ 260 #define CLK_ETHWARP_WOCPU2_EN 0 261 #define CLK_ETHWARP_WOCPU1_EN 1 262 #define CLK_ETHWARP_WOCPU0_EN 2 263 264 #endif /* _DT_BINDINGS_CLK_MT7988_H */ 265