1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 * 5 */ 6 7 #ifndef _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ 8 #define _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ 9 10 /* PLL output is enable when x=1, with x=p,q or r */ 11 #define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) 12 13 /* st,clksrc: mandatory clock source */ 14 15 #define CMD_DIV 0 16 #define CMD_MUX 1 17 #define CMD_CLK 2 18 #define CMD_RESERVED1 3 19 20 #define CMD_SHIFT 26 21 #define CMD_MASK 0xFC000000 22 #define CMD_DATA_MASK 0x03FFFFFF 23 24 #define DIV_ID_SHIFT 8 25 #define DIV_ID_MASK 0x0000FF00 26 27 #define DIV_DIVN_SHIFT 0 28 #define DIV_DIVN_MASK 0x000000FF 29 30 #define MUX_ID_SHIFT 4 31 #define MUX_ID_MASK 0x00000FF0 32 33 #define MUX_SEL_SHIFT 0 34 #define MUX_SEL_MASK 0x0000000F 35 36 #define CLK_ID_MASK GENMASK_32(19, 11) 37 #define CLK_ID_SHIFT 11 38 #define CLK_ON_MASK 0x00000400 39 #define CLK_ON_SHIFT 10 40 #define CLK_DIV_MASK GENMASK_32(9, 4) 41 #define CLK_DIV_SHIFT 4 42 #define CLK_SEL_MASK GENMASK_32(3, 0) 43 #define CLK_SEL_SHIFT 0 44 45 #define DIV_PLL1DIVP 0 46 #define DIV_PLL2DIVP 1 47 #define DIV_PLL2DIVQ 2 48 #define DIV_PLL2DIVR 3 49 #define DIV_PLL3DIVP 4 50 #define DIV_PLL3DIVQ 5 51 #define DIV_PLL3DIVR 6 52 #define DIV_PLL4DIVP 7 53 #define DIV_PLL4DIVQ 8 54 #define DIV_PLL4DIVR 9 55 #define DIV_MPU 10 56 #define DIV_AXI 11 57 #define DIV_MLAHB 12 58 #define DIV_APB1 13 59 #define DIV_APB2 14 60 #define DIV_APB3 15 61 #define DIV_APB4 16 62 #define DIV_APB5 17 63 #define DIV_APB6 18 64 #define DIV_RTC 19 65 #define DIV_MCO1 20 66 #define DIV_MCO2 21 67 #define DIV_HSI 22 68 #define DIV_TRACE 23 69 #define DIV_ETH1PTP 24 70 #define DIV_ETH2PTP 25 71 #define DIV_MAX 26 72 73 #define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ 74 ((div_id) << DIV_ID_SHIFT |\ 75 (div))) 76 77 #define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ 78 ((mux_id) << MUX_ID_SHIFT |\ 79 (sel))) 80 81 /* MCO output is enable */ 82 #define MCO_SRC(mco_id, sel) ((CMD_CLK << CMD_SHIFT) |\ 83 (((mco_id) << CLK_ID_SHIFT) |\ 84 (sel)) | CLK_ON_MASK) 85 86 #define MCO_DISABLED(mco_id) ((CMD_CLK << CMD_SHIFT) |\ 87 ((mco_id) << CLK_ID_SHIFT)) 88 89 /* CLK output is enable */ 90 #define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\ 91 (((clk_id) << CLK_ID_SHIFT) |\ 92 (sel)) | CLK_ON_MASK) 93 94 #define CLK_DISABLED(clk_id) ((CMD_CLK << CMD_SHIFT) |\ 95 ((clk_id) << CLK_ID_SHIFT)) 96 97 #define MUX_MPU 0 98 #define MUX_AXI 1 99 #define MUX_MLAHB 2 100 #define MUX_PLL12 3 101 #define MUX_PLL3 4 102 #define MUX_PLL4 5 103 #define MUX_RTC 6 104 #define MUX_MCO1 7 105 #define MUX_MCO2 8 106 #define MUX_CKPER 9 107 #define MUX_KERNEL_BEGIN 10 108 #define MUX_ADC1 10 109 #define MUX_ADC2 11 110 #define MUX_DCMIPP 12 111 #define MUX_ETH1 13 112 #define MUX_ETH2 14 113 #define MUX_FDCAN 15 114 #define MUX_FMC 16 115 #define MUX_I2C12 17 116 #define MUX_I2C3 18 117 #define MUX_I2C4 19 118 #define MUX_I2C5 20 119 #define MUX_LPTIM1 21 120 #define MUX_LPTIM2 22 121 #define MUX_LPTIM3 23 122 #define MUX_LPTIM45 24 123 #define MUX_QSPI 25 124 #define MUX_RNG1 26 125 #define MUX_SAES 27 126 #define MUX_SAI1 28 127 #define MUX_SAI2 29 128 #define MUX_SDMMC1 30 129 #define MUX_SDMMC2 31 130 #define MUX_SPDIF 32 131 #define MUX_SPI1 33 132 #define MUX_SPI23 34 133 #define MUX_SPI4 35 134 #define MUX_SPI5 36 135 #define MUX_STGEN 37 136 #define MUX_UART1 38 137 #define MUX_UART2 39 138 #define MUX_UART35 40 139 #define MUX_UART4 41 140 #define MUX_UART6 42 141 #define MUX_UART78 43 142 #define MUX_USBO 44 143 #define MUX_USBPHY 45 144 #define MUX_MAX 46 145 146 #define CLK_MPU_HSI CLKSRC(MUX_MPU, 0) 147 #define CLK_MPU_HSE CLKSRC(MUX_MPU, 1) 148 #define CLK_MPU_PLL1P CLKSRC(MUX_MPU, 2) 149 #define CLK_MPU_PLL1P_DIV CLKSRC(MUX_MPU, 3) 150 151 #define CLK_AXI_HSI CLKSRC(MUX_AXI, 0) 152 #define CLK_AXI_HSE CLKSRC(MUX_AXI, 1) 153 #define CLK_AXI_PLL2P CLKSRC(MUX_AXI, 2) 154 155 #define CLK_MLAHBS_HSI CLKSRC(MUX_MLAHB, 0) 156 #define CLK_MLAHBS_HSE CLKSRC(MUX_MLAHB, 1) 157 #define CLK_MLAHBS_CSI CLKSRC(MUX_MLAHB, 2) 158 #define CLK_MLAHBS_PLL3 CLKSRC(MUX_MLAHB, 3) 159 160 #define CLK_PLL12_HSI CLKSRC(MUX_PLL12, 0) 161 #define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1) 162 163 #define CLK_PLL3_HSI CLKSRC(MUX_PLL3, 0) 164 #define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1) 165 #define CLK_PLL3_CSI CLKSRC(MUX_PLL3, 2) 166 167 #define CLK_PLL4_HSI CLKSRC(MUX_PLL4, 0) 168 #define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1) 169 #define CLK_PLL4_CSI CLKSRC(MUX_PLL4, 2) 170 171 #define CLK_RTC_DISABLED CLK_DISABLED(RTC) 172 #define CLK_RTC_LSE CLK_SRC(RTC, 1) 173 #define CLK_RTC_LSI CLK_SRC(RTC, 2) 174 #define CLK_RTC_HSE CLK_SRC(RTC, 3) 175 176 #define CLK_MCO1_HSI CLK_SRC(CK_MCO1, 0) 177 #define CLK_MCO1_HSE CLK_SRC(CK_MCO1, 1) 178 #define CLK_MCO1_CSI CLK_SRC(CK_MCO1, 2) 179 #define CLK_MCO1_LSI CLK_SRC(CK_MCO1, 3) 180 #define CLK_MCO1_LSE CLK_SRC(CK_MCO1, 4) 181 #define CLK_MCO1_DISABLED CLK_DISABLED(CK_MCO1) 182 183 #define CLK_MCO2_MPU CLK_SRC(CK_MCO2, 0) 184 #define CLK_MCO2_AXI CLK_SRC(CK_MCO2, 1) 185 #define CLK_MCO2_MLAHB CLK_SRC(CK_MCO2, 2) 186 #define CLK_MCO2_PLL4 CLK_SRC(CK_MCO2, 3) 187 #define CLK_MCO2_HSE CLK_SRC(CK_MCO2, 4) 188 #define CLK_MCO2_HSI CLK_SRC(CK_MCO2, 5) 189 #define CLK_MCO2_DISABLED CLK_DISABLED(CK_MCO2) 190 191 #define CLK_CKPER_HSI CLKSRC(MUX_CKPER, 0) 192 #define CLK_CKPER_CSI CLKSRC(MUX_CKPER, 1) 193 #define CLK_CKPER_HSE CLKSRC(MUX_CKPER, 2) 194 #define CLK_CKPER_DISABLED CLKSRC(MUX_CKPER, 3) 195 196 #define CLK_I2C12_PCLK1 CLKSRC(MUX_I2C12, 0) 197 #define CLK_I2C12_PLL4R CLKSRC(MUX_I2C12, 1) 198 #define CLK_I2C12_HSI CLKSRC(MUX_I2C12, 2) 199 #define CLK_I2C12_CSI CLKSRC(MUX_I2C12, 3) 200 201 #define CLK_I2C3_PCLK6 CLKSRC(MUX_I2C3, 0) 202 #define CLK_I2C3_PLL4R CLKSRC(MUX_I2C3, 1) 203 #define CLK_I2C3_HSI CLKSRC(MUX_I2C3, 2) 204 #define CLK_I2C3_CSI CLKSRC(MUX_I2C3, 3) 205 206 #define CLK_I2C4_PCLK6 CLKSRC(MUX_I2C4, 0) 207 #define CLK_I2C4_PLL4R CLKSRC(MUX_I2C4, 1) 208 #define CLK_I2C4_HSI CLKSRC(MUX_I2C4, 2) 209 #define CLK_I2C4_CSI CLKSRC(MUX_I2C4, 3) 210 211 #define CLK_I2C5_PCLK6 CLKSRC(MUX_I2C5, 0) 212 #define CLK_I2C5_PLL4R CLKSRC(MUX_I2C5, 1) 213 #define CLK_I2C5_HSI CLKSRC(MUX_I2C5, 2) 214 #define CLK_I2C5_CSI CLKSRC(MUX_I2C5, 3) 215 216 #define CLK_SPI1_PLL4P CLKSRC(MUX_SPI1, 0) 217 #define CLK_SPI1_PLL3Q CLKSRC(MUX_SPI1, 1) 218 #define CLK_SPI1_I2SCKIN CLKSRC(MUX_SPI1, 2) 219 #define CLK_SPI1_CKPER CLKSRC(MUX_SPI1, 3) 220 #define CLK_SPI1_PLL3R CLKSRC(MUX_SPI1, 4) 221 222 #define CLK_SPI23_PLL4P CLKSRC(MUX_SPI23, 0) 223 #define CLK_SPI23_PLL3Q CLKSRC(MUX_SPI23, 1) 224 #define CLK_SPI23_I2SCKIN CLKSRC(MUX_SPI23, 2) 225 #define CLK_SPI23_CKPER CLKSRC(MUX_SPI23, 3) 226 #define CLK_SPI23_PLL3R CLKSRC(MUX_SPI23, 4) 227 228 #define CLK_SPI4_PCLK6 CLKSRC(MUX_SPI4, 0) 229 #define CLK_SPI4_PLL4Q CLKSRC(MUX_SPI4, 1) 230 #define CLK_SPI4_HSI CLKSRC(MUX_SPI4, 2) 231 #define CLK_SPI4_CSI CLKSRC(MUX_SPI4, 3) 232 #define CLK_SPI4_HSE CLKSRC(MUX_SPI4, 4) 233 #define CLK_SPI4_I2SCKIN CLKSRC(MUX_SPI4, 5) 234 235 #define CLK_SPI5_PCLK6 CLKSRC(MUX_SPI5, 0) 236 #define CLK_SPI5_PLL4Q CLKSRC(MUX_SPI5, 1) 237 #define CLK_SPI5_HSI CLKSRC(MUX_SPI5, 2) 238 #define CLK_SPI5_CSI CLKSRC(MUX_SPI5, 3) 239 #define CLK_SPI5_HSE CLKSRC(MUX_SPI5, 4) 240 241 #define CLK_UART1_PCLK6 CLKSRC(MUX_UART1, 0) 242 #define CLK_UART1_PLL3Q CLKSRC(MUX_UART1, 1) 243 #define CLK_UART1_HSI CLKSRC(MUX_UART1, 2) 244 #define CLK_UART1_CSI CLKSRC(MUX_UART1, 3) 245 #define CLK_UART1_PLL4Q CLKSRC(MUX_UART1, 4) 246 #define CLK_UART1_HSE CLKSRC(MUX_UART1, 5) 247 248 #define CLK_UART2_PCLK6 CLKSRC(MUX_UART2, 0) 249 #define CLK_UART2_PLL3Q CLKSRC(MUX_UART2, 1) 250 #define CLK_UART2_HSI CLKSRC(MUX_UART2, 2) 251 #define CLK_UART2_CSI CLKSRC(MUX_UART2, 3) 252 #define CLK_UART2_PLL4Q CLKSRC(MUX_UART2, 4) 253 #define CLK_UART2_HSE CLKSRC(MUX_UART2, 5) 254 255 #define CLK_UART35_PCLK1 CLKSRC(MUX_UART35, 0) 256 #define CLK_UART35_PLL4Q CLKSRC(MUX_UART35, 1) 257 #define CLK_UART35_HSI CLKSRC(MUX_UART35, 2) 258 #define CLK_UART35_CSI CLKSRC(MUX_UART35, 3) 259 #define CLK_UART35_HSE CLKSRC(MUX_UART35, 4) 260 261 #define CLK_UART4_PCLK1 CLKSRC(MUX_UART4, 0) 262 #define CLK_UART4_PLL4Q CLKSRC(MUX_UART4, 1) 263 #define CLK_UART4_HSI CLKSRC(MUX_UART4, 2) 264 #define CLK_UART4_CSI CLKSRC(MUX_UART4, 3) 265 #define CLK_UART4_HSE CLKSRC(MUX_UART4, 4) 266 267 #define CLK_UART6_PCLK2 CLKSRC(MUX_UART6, 0) 268 #define CLK_UART6_PLL4Q CLKSRC(MUX_UART6, 1) 269 #define CLK_UART6_HSI CLKSRC(MUX_UART6, 2) 270 #define CLK_UART6_CSI CLKSRC(MUX_UART6, 3) 271 #define CLK_UART6_HSE CLKSRC(MUX_UART6, 4) 272 273 #define CLK_UART78_PCLK1 CLKSRC(MUX_UART78, 0) 274 #define CLK_UART78_PLL4Q CLKSRC(MUX_UART78, 1) 275 #define CLK_UART78_HSI CLKSRC(MUX_UART78, 2) 276 #define CLK_UART78_CSI CLKSRC(MUX_UART78, 3) 277 #define CLK_UART78_HSE CLKSRC(MUX_UART78, 4) 278 279 #define CLK_LPTIM1_PCLK1 CLKSRC(MUX_LPTIM1, 0) 280 #define CLK_LPTIM1_PLL4P CLKSRC(MUX_LPTIM1, 1) 281 #define CLK_LPTIM1_PLL3Q CLKSRC(MUX_LPTIM1, 2) 282 #define CLK_LPTIM1_LSE CLKSRC(MUX_LPTIM1, 3) 283 #define CLK_LPTIM1_LSI CLKSRC(MUX_LPTIM1, 4) 284 #define CLK_LPTIM1_CKPER CLKSRC(MUX_LPTIM1, 5) 285 286 #define CLK_LPTIM2_PCLK3 CLKSRC(MUX_LPTIM2, 0) 287 #define CLK_LPTIM2_PLL4Q CLKSRC(MUX_LPTIM2, 1) 288 #define CLK_LPTIM2_CKPER CLKSRC(MUX_LPTIM2, 2) 289 #define CLK_LPTIM2_LSE CLKSRC(MUX_LPTIM2, 3) 290 #define CLK_LPTIM2_LSI CLKSRC(MUX_LPTIM2, 4) 291 292 #define CLK_LPTIM3_PCLK3 CLKSRC(MUX_LPTIM3, 0) 293 #define CLK_LPTIM3_PLL4Q CLKSRC(MUX_LPTIM3, 1) 294 #define CLK_LPTIM3_CKPER CLKSRC(MUX_LPTIM3, 2) 295 #define CLK_LPTIM3_LSE CLKSRC(MUX_LPTIM3, 3) 296 #define CLK_LPTIM3_LSI CLKSRC(MUX_LPTIM3, 4) 297 298 #define CLK_LPTIM45_PCLK3 CLKSRC(MUX_LPTIM45, 0) 299 #define CLK_LPTIM45_PLL4P CLKSRC(MUX_LPTIM45, 1) 300 #define CLK_LPTIM45_PLL3Q CLKSRC(MUX_LPTIM45, 2) 301 #define CLK_LPTIM45_LSE CLKSRC(MUX_LPTIM45, 3) 302 #define CLK_LPTIM45_LSI CLKSRC(MUX_LPTIM45, 4) 303 #define CLK_LPTIM45_CKPER CLKSRC(MUX_LPTIM45, 5) 304 305 #define CLK_SAI1_PLL4Q CLKSRC(MUX_SAI1, 0) 306 #define CLK_SAI1_PLL3Q CLKSRC(MUX_SAI1, 1) 307 #define CLK_SAI1_I2SCKIN CLKSRC(MUX_SAI1, 2) 308 #define CLK_SAI1_CKPER CLKSRC(MUX_SAI1, 3) 309 #define CLK_SAI1_PLL3R CLKSRC(MUX_SAI1, 4) 310 311 #define CLK_SAI2_PLL4Q CLKSRC(MUX_SAI2, 0) 312 #define CLK_SAI2_PLL3Q CLKSRC(MUX_SAI2, 1) 313 #define CLK_SAI2_I2SCKIN CLKSRC(MUX_SAI2, 2) 314 #define CLK_SAI2_CKPER CLKSRC(MUX_SAI2, 3) 315 #define CLK_SAI2_SPDIF CLKSRC(MUX_SAI2, 4) 316 #define CLK_SAI2_PLL3R CLKSRC(MUX_SAI2, 5) 317 318 #define CLK_FDCAN_HSE CLKSRC(MUX_FDCAN, 0) 319 #define CLK_FDCAN_PLL3Q CLKSRC(MUX_FDCAN, 1) 320 #define CLK_FDCAN_PLL4Q CLKSRC(MUX_FDCAN, 2) 321 #define CLK_FDCAN_PLL4R CLKSRC(MUX_FDCAN, 3) 322 323 #define CLK_SPDIF_PLL4P CLKSRC(MUX_SPDIF, 0) 324 #define CLK_SPDIF_PLL3Q CLKSRC(MUX_SPDIF, 1) 325 #define CLK_SPDIF_HSI CLKSRC(MUX_SPDIF, 2) 326 327 #define CLK_ADC1_PLL4R CLKSRC(MUX_ADC1, 0) 328 #define CLK_ADC1_CKPER CLKSRC(MUX_ADC1, 1) 329 #define CLK_ADC1_PLL3Q CLKSRC(MUX_ADC1, 2) 330 331 #define CLK_ADC2_PLL4R CLKSRC(MUX_ADC2, 0) 332 #define CLK_ADC2_CKPER CLKSRC(MUX_ADC2, 1) 333 #define CLK_ADC2_PLL3Q CLKSRC(MUX_ADC2, 2) 334 335 #define CLK_SDMMC1_HCLK6 CLKSRC(MUX_SDMMC1, 0) 336 #define CLK_SDMMC1_PLL3R CLKSRC(MUX_SDMMC1, 1) 337 #define CLK_SDMMC1_PLL4P CLKSRC(MUX_SDMMC1, 2) 338 #define CLK_SDMMC1_HSI CLKSRC(MUX_SDMMC1, 3) 339 340 #define CLK_SDMMC2_HCLK6 CLKSRC(MUX_SDMMC2, 0) 341 #define CLK_SDMMC2_PLL3R CLKSRC(MUX_SDMMC2, 1) 342 #define CLK_SDMMC2_PLL4P CLKSRC(MUX_SDMMC2, 2) 343 #define CLK_SDMMC2_HSI CLKSRC(MUX_SDMMC2, 3) 344 345 #define CLK_ETH1_PLL4P CLKSRC(MUX_ETH1, 0) 346 #define CLK_ETH1_PLL3Q CLKSRC(MUX_ETH1, 1) 347 348 #define CLK_ETH2_PLL4P CLKSRC(MUX_ETH2, 0) 349 #define CLK_ETH2_PLL3Q CLKSRC(MUX_ETH2, 1) 350 351 #define CLK_USBPHY_HSE CLKSRC(MUX_USBPHY, 0) 352 #define CLK_USBPHY_PLL4R CLKSRC(MUX_USBPHY, 1) 353 #define CLK_USBPHY_HSE_DIV2 CLKSRC(MUX_USBPHY, 2) 354 355 #define CLK_USBO_PLL4R CLKSRC(MUX_USBO, 0) 356 #define CLK_USBO_USBPHY CLKSRC(MUX_USBO, 1) 357 358 #define CLK_QSPI_ACLK CLKSRC(MUX_QSPI, 0) 359 #define CLK_QSPI_PLL3R CLKSRC(MUX_QSPI, 1) 360 #define CLK_QSPI_PLL4P CLKSRC(MUX_QSPI, 2) 361 #define CLK_QSPI_CKPER CLKSRC(MUX_QSPI, 3) 362 363 #define CLK_FMC_ACLK CLKSRC(MUX_FMC, 0) 364 #define CLK_FMC_PLL3R CLKSRC(MUX_FMC, 1) 365 #define CLK_FMC_PLL4P CLKSRC(MUX_FMC, 2) 366 #define CLK_FMC_CKPER CLKSRC(MUX_FMC, 3) 367 368 #define CLK_RNG1_CSI CLKSRC(MUX_RNG1, 0) 369 #define CLK_RNG1_PLL4R CLKSRC(MUX_RNG1, 1) 370 /* WARNING: POSITION 2 OF RNG1 MUX IS RESERVED */ 371 #define CLK_RNG1_LSI CLKSRC(MUX_RNG1, 3) 372 373 #define CLK_STGEN_HSI CLKSRC(MUX_STGEN, 0) 374 #define CLK_STGEN_HSE CLKSRC(MUX_STGEN, 1) 375 376 #define CLK_DCMIPP_ACLK CLKSRC(MUX_DCMIPP, 0) 377 #define CLK_DCMIPP_PLL2Q CLKSRC(MUX_DCMIPP, 1) 378 #define CLK_DCMIPP_PLL4P CLKSRC(MUX_DCMIPP, 2) 379 #define CLK_DCMIPP_CKPER CLKSRC(MUX_DCMIPP, 3) 380 381 #define CLK_SAES_AXI CLKSRC(MUX_SAES, 0) 382 #define CLK_SAES_CKPER CLKSRC(MUX_SAES, 1) 383 #define CLK_SAES_PLL4R CLKSRC(MUX_SAES, 2) 384 #define CLK_SAES_LSI CLKSRC(MUX_SAES, 3) 385 386 /* PLL output is enable when x=1, with x=p,q or r */ 387 #define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) 388 389 /* define for st,pll /csg */ 390 #define SSCG_MODE_CENTER_SPREAD 0 391 #define SSCG_MODE_DOWN_SPREAD 1 392 393 /* define for st,drive */ 394 #define LSEDRV_LOWEST 0 395 #define LSEDRV_MEDIUM_LOW 1 396 #define LSEDRV_MEDIUM_HIGH 2 397 #define LSEDRV_HIGHEST 3 398 399 #endif 400