1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2025 Altera Corporation <www.altera.com> 4 */ 5 6 #ifndef _DW_I3C_H_ 7 #define _DW_I3C_H_ 8 9 #include <clk.h> 10 #include <i3c.h> 11 #include <reset.h> 12 #include <dm/device.h> 13 #include <linux/bitops.h> 14 #include <linux/bitfield.h> 15 #include <linker_lists.h> 16 #include <linux/i3c/master.h> 17 18 #define DEVICE_CTRL 0x0 19 #define DEV_CTRL_ENABLE BIT(31) 20 #define DEV_CTRL_RESUME BIT(30) 21 #define DEV_CTRL_HOT_JOIN_NACK BIT(8) 22 #define DEV_CTRL_I2C_SLAVE_PRESENT BIT(7) 23 24 #define DEVICE_ADDR 0x4 25 #define DEV_ADDR_DYNAMIC_ADDR_VALID BIT(31) 26 #define DEV_ADDR_DYNAMIC(x) (((x) << 16) & GENMASK(22, 16)) 27 28 #define HW_CAPABILITY 0x8 29 #define COMMAND_QUEUE_PORT 0xc 30 #define COMMAND_PORT_TOC BIT(30) 31 #define COMMAND_PORT_READ_TRANSFER BIT(28) 32 #define COMMAND_PORT_SDAP BIT(27) 33 #define COMMAND_PORT_ROC BIT(26) 34 #define COMMAND_PORT_SPEED(x) (((x) << 21) & GENMASK(23, 21)) 35 #define COMMAND_PORT_DEV_INDEX(x) (((x) << 16) & GENMASK(20, 16)) 36 #define COMMAND_PORT_CP BIT(15) 37 #define COMMAND_PORT_CMD(x) (((x) << 7) & GENMASK(14, 7)) 38 #define COMMAND_PORT_TID(x) (((x) << 3) & GENMASK(6, 3)) 39 40 #define COMMAND_PORT_ARG_DATA_LEN(x) (((x) << 16) & GENMASK(31, 16)) 41 #define COMMAND_PORT_ARG_DATA_LEN_MAX 65536 42 #define COMMAND_PORT_TRANSFER_ARG 0x01 43 44 #define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24)) 45 #define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16)) 46 #define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8)) 47 #define COMMAND_PORT_SDA_BYTE_STRB_3 BIT(5) 48 #define COMMAND_PORT_SDA_BYTE_STRB_2 BIT(4) 49 #define COMMAND_PORT_SDA_BYTE_STRB_1 BIT(3) 50 #define COMMAND_PORT_SHORT_DATA_ARG 0x02 51 52 #define COMMAND_PORT_DEV_COUNT(x) (((x) << 21) & GENMASK(25, 21)) 53 #define COMMAND_PORT_ADDR_ASSGN_CMD 0x03 54 55 #define RESPONSE_QUEUE_PORT 0x10 56 #define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28) 57 #define RESPONSE_NO_ERROR 0 58 #define RESPONSE_ERROR_CRC 1 59 #define RESPONSE_ERROR_PARITY 2 60 #define RESPONSE_ERROR_FRAME 3 61 #define RESPONSE_ERROR_IBA_NACK 4 62 #define RESPONSE_ERROR_ADDRESS_NACK 5 63 #define RESPONSE_ERROR_OVER_UNDER_FLOW 6 64 #define RESPONSE_ERROR_TRANSF_ABORT 8 65 #define RESPONSE_ERROR_I2C_W_NACK_ERR 9 66 #define RESPONSE_PORT_TID(x) (((x) & GENMASK(27, 24)) >> 24) 67 #define RESPONSE_PORT_DATA_LEN(x) ((x) & GENMASK(15, 0)) 68 69 #define RX_TX_DATA_PORT 0x14 70 #define IBI_QUEUE_STATUS 0x18 71 #define QUEUE_THLD_CTRL 0x1c 72 #define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8) 73 #define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8) 74 75 #define DATA_BUFFER_THLD_CTRL 0x20 76 #define DATA_BUFFER_THLD_CTRL_RX_BUF GENMASK(11, 8) 77 78 #define IBI_QUEUE_CTRL 0x24 79 #define IBI_MR_REQ_REJECT 0x2C 80 #define IBI_SIR_REQ_REJECT 0x30 81 #define IBI_REQ_REJECT_ALL GENMASK(31, 0) 82 83 #define RESET_CTRL 0x34 84 #define RESET_CTRL_IBI_QUEUE BIT(5) 85 #define RESET_CTRL_RX_FIFO BIT(4) 86 #define RESET_CTRL_TX_FIFO BIT(3) 87 #define RESET_CTRL_RESP_QUEUE BIT(2) 88 #define RESET_CTRL_CMD_QUEUE BIT(1) 89 #define RESET_CTRL_SOFT BIT(0) 90 91 #define SLV_EVENT_CTRL 0x38 92 #define INTR_STATUS 0x3c 93 #define INTR_STATUS_EN 0x40 94 #define INTR_SIGNAL_EN 0x44 95 #define INTR_FORCE 0x48 96 #define INTR_BUSOWNER_UPDATE_STAT BIT(13) 97 #define INTR_IBI_UPDATED_STAT BIT(12) 98 #define INTR_READ_REQ_RECV_STAT BIT(11) 99 #define INTR_DEFSLV_STAT BIT(10) 100 #define INTR_TRANSFER_ERR_STAT BIT(9) 101 #define INTR_DYN_ADDR_ASSGN_STAT BIT(8) 102 #define INTR_CCC_UPDATED_STAT BIT(6) 103 #define INTR_TRANSFER_ABORT_STAT BIT(5) 104 #define INTR_RESP_READY_STAT BIT(4) 105 #define INTR_CMD_QUEUE_READY_STAT BIT(3) 106 #define INTR_IBI_THLD_STAT BIT(2) 107 #define INTR_RX_THLD_STAT BIT(1) 108 #define INTR_TX_THLD_STAT BIT(0) 109 #define INTR_ALL (INTR_BUSOWNER_UPDATE_STAT | \ 110 INTR_IBI_UPDATED_STAT | \ 111 INTR_READ_REQ_RECV_STAT | \ 112 INTR_DEFSLV_STAT | \ 113 INTR_TRANSFER_ERR_STAT | \ 114 INTR_DYN_ADDR_ASSGN_STAT | \ 115 INTR_CCC_UPDATED_STAT | \ 116 INTR_TRANSFER_ABORT_STAT | \ 117 INTR_RESP_READY_STAT | \ 118 INTR_CMD_QUEUE_READY_STAT | \ 119 INTR_IBI_THLD_STAT | \ 120 INTR_TX_THLD_STAT | \ 121 INTR_RX_THLD_STAT) 122 123 #define INTR_MASTER_MASK (INTR_TRANSFER_ERR_STAT | \ 124 INTR_RESP_READY_STAT) 125 126 #define QUEUE_STATUS_LEVEL 0x4c 127 #define QUEUE_STATUS_IBI_STATUS_CNT(x) (((x) & GENMASK(28, 24)) >> 24) 128 #define QUEUE_STATUS_IBI_BUF_BLR(x) (((x) & GENMASK(23, 16)) >> 16) 129 #define QUEUE_STATUS_LEVEL_RESP(x) (((x) & GENMASK(15, 8)) >> 8) 130 #define QUEUE_STATUS_LEVEL_CMD(x) ((x) & GENMASK(7, 0)) 131 132 #define DATA_BUFFER_STATUS_LEVEL 0x50 133 #define DATA_BUFFER_STATUS_LEVEL_TX(x) ((x) & GENMASK(7, 0)) 134 135 #define PRESENT_STATE 0x54 136 #define CCC_DEVICE_STATUS 0x58 137 #define DEVICE_ADDR_TABLE_POINTER 0x5c 138 #define DEVICE_ADDR_TABLE_DEPTH(x) (((x) & GENMASK(31, 16)) >> 16) 139 #define DEVICE_ADDR_TABLE_ADDR(x) ((x) & GENMASK(7, 0)) 140 141 #define DEV_CHAR_TABLE_POINTER 0x60 142 #define VENDOR_SPECIFIC_REG_POINTER 0x6c 143 #define SLV_PID_VALUE 0x74 144 #define SLV_CHAR_CTRL 0x78 145 #define SLV_MAX_LEN 0x7c 146 #define MAX_READ_TURNAROUND 0x80 147 #define MAX_DATA_SPEED 0x84 148 #define SLV_DEBUG_STATUS 0x88 149 #define SLV_INTR_REQ 0x8c 150 #define DEVICE_CTRL_EXTENDED 0xb0 151 #define SCL_I3C_OD_TIMING 0xb4 152 #define SCL_I3C_PP_TIMING 0xb8 153 #define SCL_I3C_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16)) 154 #define SCL_I3C_TIMING_LCNT(x) ((x) & GENMASK(7, 0)) 155 #define SCL_I3C_TIMING_CNT_MIN 5 156 157 #define SCL_I2C_FM_TIMING 0xbc 158 #define SCL_I2C_FM_TIMING_HCNT(x) (((x) << 16) & GENMASK(31, 16)) 159 #define SCL_I2C_FM_TIMING_LCNT(x) ((x) & GENMASK(15, 0)) 160 161 #define SCL_I2C_FMP_TIMING 0xc0 162 #define SCL_I2C_FMP_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16)) 163 #define SCL_I2C_FMP_TIMING_LCNT(x) ((x) & GENMASK(15, 0)) 164 165 #define SCL_EXT_LCNT_TIMING 0xc8 166 #define SCL_EXT_LCNT_4(x) (((x) << 24) & GENMASK(31, 24)) 167 #define SCL_EXT_LCNT_3(x) (((x) << 16) & GENMASK(23, 16)) 168 #define SCL_EXT_LCNT_2(x) (((x) << 8) & GENMASK(15, 8)) 169 #define SCL_EXT_LCNT_1(x) ((x) & GENMASK(7, 0)) 170 171 #define SCL_EXT_TERMN_LCNT_TIMING 0xcc 172 #define BUS_FREE_TIMING 0xd4 173 #define BUS_I3C_MST_FREE(x) ((x) & GENMASK(15, 0)) 174 175 #define BUS_IDLE_TIMING 0xd8 176 #define I3C_VER_ID 0xe0 177 #define I3C_VER_TYPE 0xe4 178 #define EXTENDED_CAPABILITY 0xe8 179 #define SLAVE_CONFIG 0xec 180 181 #define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31) 182 #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) (((x) << 16) & GENMASK(23, 16)) 183 #define DEV_ADDR_TABLE_STATIC_ADDR(x) ((x) & GENMASK(6, 0)) 184 #define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2)) 185 186 #define MAX_DEVS 32 187 188 #define I3C_BUS_SDR1_SCL_RATE 8000000 189 #define I3C_BUS_SDR2_SCL_RATE 6000000 190 #define I3C_BUS_SDR3_SCL_RATE 4000000 191 #define I3C_BUS_SDR4_SCL_RATE 2000000 192 #define I3C_BUS_I2C_FM_TLOW_MIN_NS 1300 193 #define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500 194 #define I3C_BUS_THIGH_MAX_NS 41 195 196 #define XFER_TIMEOUT (msecs_to_jiffies(1000)) 197 #define readl_poll_timeout_atomic readl_poll_sleep_timeout 198 #define STRUCT_SZ(struct, count) (sizeof(struct) * (count)) 199 200 #define I3C_MSG_READ 1 201 #define I3C_MSG_WRITE 0 202 #define POLL_SUCCESS 0 203 204 struct dw_i3c_master_caps { 205 u8 cmdfifodepth; 206 u8 datafifodepth; 207 }; 208 209 struct dw_i3c_cmd { 210 u32 cmd_lo; 211 u32 cmd_hi; 212 u16 tx_len; 213 const void *tx_buf; 214 u16 rx_len; 215 void *rx_buf; 216 u8 error; 217 }; 218 219 struct dw_i3c_xfer { 220 struct list_head node; 221 int ret; 222 unsigned int ncmds; 223 struct dw_i3c_cmd cmds[16]; 224 }; 225 226 struct dw_i3c_master { 227 struct i3c_master_controller base; 228 u16 maxdevs; 229 u16 datstartaddr; 230 u32 free_pos; 231 struct { 232 struct list_head list; 233 struct dw_i3c_xfer *cur; 234 spinlock_t lock; /* spinlock for i3c transfer */ 235 } xferqueue; 236 struct dw_i3c_master_caps caps; 237 void __iomem *regs; 238 struct reset_ctl_bulk resets; 239 struct clk core_clk; 240 char version[5]; 241 char type[5]; 242 u8 addrs[MAX_DEVS]; 243 bool first_broadcast; 244 struct i3c_dev_desc *i3cdev[I3C_BUS_MAX_DEVS]; 245 u16 num_i3cdevs; 246 }; 247 248 struct dw_i3c_i2c_dev_data { 249 u8 index; 250 }; 251 252 #endif /*_DW_I3C_H_*/ 253