1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * (C) Copyright 2012 SAMSUNG Electronics
4 * Jaehoon Chung <jh80.chung@samsung.com>
5 */
6
7 #ifndef __DWMMC_HW_H
8 #define __DWMMC_HW_H
9
10 #include <asm/io.h>
11 #include <mmc.h>
12 #include <linux/bitops.h>
13
14 #define DWMCI_CTRL 0x000
15 #define DWMCI_PWREN 0x004
16 #define DWMCI_CLKDIV 0x008
17 #define DWMCI_CLKSRC 0x00c
18 #define DWMCI_CLKENA 0x010
19 #define DWMCI_TMOUT 0x014
20 #define DWMCI_CTYPE 0x018
21 #define DWMCI_BLKSIZ 0x01c
22 #define DWMCI_BYTCNT 0x020
23 #define DWMCI_INTMASK 0x024
24 #define DWMCI_CMDARG 0x028
25 #define DWMCI_CMD 0x02c
26 #define DWMCI_RESP0 0x030
27 #define DWMCI_RESP1 0x034
28 #define DWMCI_RESP2 0x038
29 #define DWMCI_RESP3 0x03c
30 #define DWMCI_MINTSTS 0x040
31 #define DWMCI_RINTSTS 0x044
32 #define DWMCI_STATUS 0x048
33 #define DWMCI_FIFOTH 0x04c
34 #define DWMCI_CDETECT 0x050
35 #define DWMCI_WRTPRT 0x054
36 #define DWMCI_GPIO 0x058
37 #define DWMCI_TCMCNT 0x05c
38 #define DWMCI_TBBCNT 0x060
39 #define DWMCI_DEBNCE 0x064
40 #define DWMCI_USRID 0x068
41 #define DWMCI_VERID 0x06c
42 #define DWMCI_HCON 0x070
43 #define DWMCI_UHS_REG 0x074
44 #define DWMCI_BMOD 0x080
45 #define DWMCI_PLDMND 0x084
46 #define DWMCI_DATA 0x200
47 /* Registers to support IDMAC 32-bit address mode */
48 #define DWMCI_DBADDR 0x088
49 #define DWMCI_IDSTS 0x08c
50 #define DWMCI_IDINTEN 0x090
51 #define DWMCI_DSCADDR 0x094
52 #define DWMCI_BUFADDR 0x098
53 /* Registers to support IDMAC 64-bit address mode */
54 #define DWMCI_DBADDRL 0x088
55 #define DWMCI_DBADDRU 0x08c
56 #define DWMCI_IDSTS64 0x090
57 #define DWMCI_IDINTEN64 0x094
58 #define DWMCI_DSCADDRL 0x098
59 #define DWMCI_DSCADDRU 0x09c
60 #define DWMCI_BUFADDRL 0x0a0
61 #define DWMCI_BUFADDRU 0x0a4
62
63 /* Interrupt Mask register */
64 #define DWMCI_INTMSK_ALL 0xffffffff
65 #define DWMCI_INTMSK_RE BIT(1)
66 #define DWMCI_INTMSK_CDONE BIT(2)
67 #define DWMCI_INTMSK_DTO BIT(3)
68 #define DWMCI_INTMSK_TXDR BIT(4)
69 #define DWMCI_INTMSK_RXDR BIT(5)
70 #define DWMCI_INTMSK_RCRC BIT(6)
71 #define DWMCI_INTMSK_DCRC BIT(7)
72 #define DWMCI_INTMSK_RTO BIT(8)
73 #define DWMCI_INTMSK_DRTO BIT(9)
74 #define DWMCI_INTMSK_HTO BIT(10)
75 #define DWMCI_INTMSK_FRUN BIT(11)
76 #define DWMCI_INTMSK_HLE BIT(12)
77 #define DWMCI_INTMSK_SBE BIT(13)
78 #define DWMCI_INTMSK_ACD BIT(14)
79 #define DWMCI_INTMSK_EBE BIT(15)
80
81 /* Raw interrupt register */
82 #define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | \
83 DWMCI_INTMSK_HLE | DWMCI_INTMSK_FRUN | \
84 DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
85 #define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
86
87 /* CTRL register */
88 #define DWMCI_CTRL_RESET BIT(0)
89 #define DWMCI_CTRL_FIFO_RESET BIT(1)
90 #define DWMCI_CTRL_DMA_RESET BIT(2)
91 #define DWMCI_DMA_EN BIT(5)
92 #define DWMCI_CTRL_SEND_AS_CCSD BIT(10)
93 #define DWMCI_IDMAC_EN BIT(25)
94 #define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
95 DWMCI_CTRL_DMA_RESET)
96
97 /* CMD register */
98 #define DWMCI_CMD_RESP_EXP BIT(6)
99 #define DWMCI_CMD_RESP_LENGTH BIT(7)
100 #define DWMCI_CMD_CHECK_CRC BIT(8)
101 #define DWMCI_CMD_DATA_EXP BIT(9)
102 #define DWMCI_CMD_RW BIT(10)
103 #define DWMCI_CMD_SEND_STOP BIT(12)
104 #define DWMCI_CMD_ABORT_STOP BIT(14)
105 #define DWMCI_CMD_PRV_DAT_WAIT BIT(13)
106 #define DWMCI_CMD_UPD_CLK BIT(21)
107 #define DWMCI_CMD_USE_HOLD_REG BIT(29)
108 #define DWMCI_CMD_START BIT(31)
109
110 /* CLKENA register */
111 #define DWMCI_CLKEN_ENABLE BIT(0)
112 #define DWMCI_CLKEN_LOW_PWR BIT(16)
113
114 /* Card type register */
115 #define DWMCI_CTYPE_1BIT 0
116 #define DWMCI_CTYPE_4BIT BIT(0)
117 #define DWMCI_CTYPE_8BIT BIT(16)
118
119 /* Status register */
120 #define DWMCI_FIFO_EMPTY BIT(2)
121 #define DWMCI_FIFO_FULL BIT(3)
122 #define DWMCI_BUSY BIT(9)
123 #define DWMCI_FIFO_MASK 0x1fff
124 #define DWMCI_FIFO_SHIFT 17
125
126 /* FIFOTH register */
127 #define MSIZE(x) ((x) << 28)
128 #define RX_WMARK(x) ((x) << 16)
129 #define TX_WMARK(x) (x)
130 #define RX_WMARK_SHIFT 16
131 #define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
132
133 #define DWMCI_IDMAC_OWN BIT(31)
134 #define DWMCI_IDMAC_CH BIT(4)
135 #define DWMCI_IDMAC_FS BIT(3)
136 #define DWMCI_IDMAC_LD BIT(2)
137
138 /* Bus Mode register */
139 #define DWMCI_BMOD_IDMAC_RESET BIT(0)
140 #define DWMCI_BMOD_IDMAC_FB BIT(1)
141 #define DWMCI_BMOD_IDMAC_EN BIT(7)
142
143 /* UHS register */
144 #define DWMCI_DDR_MODE BIT(16)
145
146 /* Internal IDMAC interrupt defines */
147 #define DWMCI_IDINTEN_RI BIT(1)
148 #define DWMCI_IDINTEN_TI BIT(0)
149 #define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | DWMCI_IDINTEN_RI)
150
151 /**
152 * struct dwmci_idmac_regs - Offsets of IDMAC registers
153 *
154 * @dbaddrl: Descriptor base address, lower 32 bits
155 * @dbaddru: Descriptor base address, upper 32 bits
156 * @idsts: Internal DMA status
157 * @idinten: Internal DMA interrupt enable
158 * @dscaddrl: IDMAC descriptor address, lower 32 bits
159 * @dscaddru: IDMAC descriptor address, upper 32 bits
160 * @bufaddrl: Current data buffer address, lower 32 bits
161 * @bufaddru: Current data buffer address, upper 32 bits
162 */
163 struct dwmci_idmac_regs {
164 u32 dbaddrl;
165 u32 dbaddru;
166 u32 idsts;
167 u32 idinten;
168 u32 dscaddrl;
169 u32 dscaddru;
170 u32 bufaddrl;
171 u32 bufaddru;
172 };
173
174 /**
175 * struct dwmci_host - Information about a designware MMC host
176 *
177 * @name: Device name
178 * @ioaddr: Base I/O address of controller
179 * @caps: Capabilities - see MMC_MODE_...
180 * @clock: Current clock frequency (after internal divider), Hz
181 * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL
182 * @dev_index: Arbitrary device index for use by controller
183 * @dev_id: Arbitrary device ID for use by controller
184 * @buswidth: Bus width in bits (8 or 4)
185 * @fifo_depth: Depth of FIFO, bytes (or 0 for automatic detection)
186 * @mmc: Pointer to generic MMC structure for this device
187 * @priv: Private pointer for use by controller
188 * @clksel: (Optional) Platform function to run when speed/width is changed
189 * @board_init: (Optional) Platform function to run on init
190 * @cfg: Internal MMC configuration, for !CONFIG_BLK cases
191 * @fifo_mode: Use FIFO mode (not DMA) to read and write data
192 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not
193 * @regs: Registers that can vary for different DW MMC block versions
194 */
195 struct dwmci_host {
196 const char *name;
197 void *ioaddr;
198 unsigned int caps;
199 unsigned int clock;
200 unsigned int bus_hz;
201 int dev_index;
202 int dev_id;
203 int buswidth;
204 u32 fifo_depth;
205 struct mmc *mmc;
206 void *priv;
207
208 int (*clksel)(struct dwmci_host *host);
209 void (*board_init)(struct dwmci_host *host);
210 /**
211 * @get_mmc_clk: (Optional) Platform function to get/set a particular
212 * MMC clock frequency
213 *
214 * @host: DWMMC host
215 * @freq: Frequency the host is trying to achieve
216 *
217 * This is used to request the current clock frequency of the clock
218 * that drives the DWMMC peripheral. The caller will then use this
219 * information to work out the divider it needs to achieve the
220 * required MMC bus clock frequency. If you want to handle the
221 * clock external to DWMMC, use @freq to select the frequency and
222 * return that value too. Then DWMMC will put itself in bypass mode.
223 */
224 unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
225
226 #ifndef CONFIG_BLK
227 struct mmc_config cfg;
228 #endif
229
230 bool fifo_mode;
231 bool dma_64bit_address;
232 const struct dwmci_idmac_regs *regs;
233 };
234
dwmci_writel(struct dwmci_host * host,int reg,u32 val)235 static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
236 {
237 writel(val, host->ioaddr + reg);
238 }
239
dwmci_writew(struct dwmci_host * host,int reg,u16 val)240 static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
241 {
242 writew(val, host->ioaddr + reg);
243 }
244
dwmci_writeb(struct dwmci_host * host,int reg,u8 val)245 static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
246 {
247 writeb(val, host->ioaddr + reg);
248 }
249
dwmci_readl(struct dwmci_host * host,int reg)250 static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
251 {
252 return readl(host->ioaddr + reg);
253 }
254
dwmci_readw(struct dwmci_host * host,int reg)255 static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
256 {
257 return readw(host->ioaddr + reg);
258 }
259
dwmci_readb(struct dwmci_host * host,int reg)260 static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
261 {
262 return readb(host->ioaddr + reg);
263 }
264
265 #ifdef CONFIG_BLK
266
267 /**
268 * dwmci_setup_cfg() - Set up the configuration for DWMMC
269 * @cfg: Configuration structure to fill in (generally &plat->mmc)
270 * @host: DWMMC host
271 * @max_clk: Maximum supported clock speed in Hz (e.g. 150000000)
272 * @min_clk: Minimum supported clock speed in Hz (e.g. 400000)
273 *
274 * This is used to set up a DWMMC device when you are using CONFIG_BLK.
275 *
276 * This should be called from your MMC driver's probe() method once you have
277 * the information required.
278 *
279 * Generally your driver will have a platform data structure which holds both
280 * the configuration (struct mmc_config) and the MMC device info (struct mmc).
281 * For example:
282 *
283 * struct rockchip_mmc_plat {
284 * struct mmc_config cfg;
285 * struct mmc mmc;
286 * };
287 *
288 * ...
289 *
290 * Inside U_BOOT_DRIVER():
291 * .plat_auto = sizeof(struct rockchip_mmc_plat),
292 *
293 * To access platform data:
294 * struct rockchip_mmc_plat *plat = dev_get_plat(dev);
295 *
296 * See rockchip_dw_mmc.c for an example.
297 */
298 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
299 u32 max_clk, u32 min_clk);
300
301 /**
302 * dwmci_bind() - Set up a new MMC block device
303 * @dev: Device to set up
304 * @mmc: Pointer to mmc structure (normally &plat->mmc)
305 * @cfg: Empty configuration structure (generally &plat->cfg). This is
306 * normally all zeroes at this point. The only purpose of passing
307 * this in is to set mmc->cfg to it.
308 *
309 * This is used to set up a DWMMC block device when you are using CONFIG_BLK.
310 * It should be called from your driver's bind() method.
311 *
312 * See rockchip_dw_mmc.c for an example.
313 *
314 * Return: 0 if OK, -ve if the block device could not be created
315 */
316 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
317
318 #else
319
320 /**
321 * add_dwmci() - Add a new DWMMC interface
322 * @host: DWMMC host structure
323 * @max_clk: Maximum supported clock speed in Hz (e.g. 150000000)
324 * @min_clk: Minimum supported clock speed in Hz (e.g. 400000)
325 *
326 * This is used when you are not using CONFIG_BLK. Convert your driver over!
327 *
328 * Return: 0 if OK, -ve on error
329 */
330 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
331
332 #endif /* !CONFIG_BLK */
333
334 #ifdef CONFIG_DM_MMC
335 /* Export the operations to drivers */
336 int dwmci_probe(struct udevice *dev);
337 extern const struct dm_mmc_ops dm_dwmci_ops;
338 #endif
339
340 #endif /* __DWMMC_HW_H */
341