1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2018 NXP
4 */
5
6 #ifndef _SC_SCI_H
7 #define _SC_SCI_H
8
9 #include <log.h>
10 #include <firmware/imx/sci/types.h>
11 #include <firmware/imx/sci/svc/misc/api.h>
12 #include <firmware/imx/sci/svc/pad/api.h>
13 #include <firmware/imx/sci/svc/pm/api.h>
14 #include <firmware/imx/sci/svc/rm/api.h>
15 #include <firmware/imx/sci/svc/seco/api.h>
16 #include <firmware/imx/sci/svc/timer/api.h>
17 #include <firmware/imx/sci/rpc.h>
18 #include <dt-bindings/soc/imx_rsrc.h>
19 #include <linux/errno.h>
20
sc_err_to_linux(sc_err_t err)21 static inline int sc_err_to_linux(sc_err_t err)
22 {
23 int ret;
24
25 switch (err) {
26 case SC_ERR_NONE:
27 return 0;
28 case SC_ERR_VERSION:
29 case SC_ERR_CONFIG:
30 case SC_ERR_PARM:
31 ret = -EINVAL;
32 break;
33 case SC_ERR_NOACCESS:
34 case SC_ERR_LOCKED:
35 case SC_ERR_UNAVAILABLE:
36 ret = -EACCES;
37 break;
38 case SC_ERR_NOTFOUND:
39 case SC_ERR_NOPOWER:
40 ret = -ENODEV;
41 break;
42 case SC_ERR_IPC:
43 ret = -EIO;
44 break;
45 case SC_ERR_BUSY:
46 ret = -EBUSY;
47 break;
48 case SC_ERR_FAIL:
49 ret = -EIO;
50 break;
51 default:
52 ret = 0;
53 break;
54 }
55
56 debug("%s %d %d\n", __func__, err, ret);
57
58 return ret;
59 }
60
61 #if IS_ENABLED(CONFIG_IMX8)
62 /* PM API*/
63 int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
64 sc_pm_power_mode_t mode);
65 int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
66 sc_pm_power_mode_t *mode);
67 int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
68 sc_pm_clock_rate_t *rate);
69 int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
70 sc_pm_clock_rate_t *rate);
71 int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
72 sc_bool_t enable, sc_bool_t autog);
73 int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
74 sc_pm_clk_parent_t parent);
75 int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
76 sc_faddr_t address);
77 void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type);
78 int sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason);
79 sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
80 int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource);
81
82 /* MISC API */
83 int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
84 sc_ctrl_t ctrl, u32 val);
85 int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
86 u32 *val);
87 void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
88 void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
89 int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx);
90 void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
91 int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
92 int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
93 s16 *celsius, s8 *tenths);
94 void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status);
95
96 /* RM API */
97 sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
98 int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start,
99 sc_faddr_t addr_end);
100 int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
101 sc_rm_pt_t pt, sc_rm_perm_t perm);
102 int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start,
103 sc_faddr_t *addr_end);
104 sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
105 int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
106 sc_bool_t isolated, sc_bool_t restricted,
107 sc_bool_t grant, sc_bool_t coherent);
108 int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt);
109 int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt);
110 int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent);
111 int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
112 int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
113 sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
114 int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource,
115 sc_rm_pt_t *pt);
116
117 /* PAD API */
118 int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
119 int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
120
121 /* SMMU API */
122 int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
123
124 /* Timer API */
125 int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window);
126 int sc_timer_control_siemens_pmic_wdog(sc_ipc_t ipc, u8 cmd);
127
128 /* SECO API */
129 int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
130 sc_faddr_t addr);
131 int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change);
132 int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l,
133 u32 *uid_h);
134 void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
135 int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
136 int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
137 int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
138 sc_faddr_t export_addr, u16 max_size);
139 int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size);
140 int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock);
141 int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
142 u16 msg_size, sc_faddr_t dst_addr, u16 dst_size);
143 int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data);
144 int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access,
145 u32 *data0, u32 *data1, u32 *data2, u32 *data3,
146 u32 *data4, u8 size);
147 #else
148 /* PM API*/
sc_pm_set_resource_power_mode(sc_ipc_t ipc,sc_rsrc_t resource,sc_pm_power_mode_t mode)149 static inline int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
150 sc_pm_power_mode_t mode)
151 {
152 return -EOPNOTSUPP;
153 }
154
sc_pm_get_resource_power_mode(sc_ipc_t ipc,sc_rsrc_t resource,sc_pm_power_mode_t * mode)155 static inline int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
156 sc_pm_power_mode_t *mode)
157 {
158 return -EOPNOTSUPP;
159 }
160
sc_pm_set_clock_rate(sc_ipc_t ipc,sc_rsrc_t resource,sc_pm_clk_t clk,sc_pm_clock_rate_t * rate)161 static inline int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
162 sc_pm_clock_rate_t *rate)
163 {
164 return -EOPNOTSUPP;
165 }
166
sc_pm_get_clock_rate(sc_ipc_t ipc,sc_rsrc_t resource,sc_pm_clk_t clk,sc_pm_clock_rate_t * rate)167 static inline int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
168 sc_pm_clock_rate_t *rate)
169 {
170 return -EOPNOTSUPP;
171 }
172
sc_pm_clock_enable(sc_ipc_t ipc,sc_rsrc_t resource,sc_pm_clk_t clk,sc_bool_t enable,sc_bool_t autog)173 static inline int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
174 sc_bool_t enable, sc_bool_t autog)
175 {
176 return -EOPNOTSUPP;
177 }
178
sc_pm_set_clock_parent(sc_ipc_t ipc,sc_rsrc_t resource,sc_pm_clk_t clk,sc_pm_clk_parent_t parent)179 static inline int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
180 sc_pm_clk_parent_t parent)
181 {
182 return -EOPNOTSUPP;
183 }
184
sc_pm_cpu_start(sc_ipc_t ipc,sc_rsrc_t resource,sc_bool_t enable,sc_faddr_t address)185 static inline int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
186 sc_faddr_t address)
187 {
188 return -EOPNOTSUPP;
189 }
190
sc_pm_is_partition_started(sc_ipc_t ipc,sc_rm_pt_t pt)191 static inline sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt)
192 {
193 return false;
194 }
195
sc_pm_resource_reset(sc_ipc_t ipc,sc_rsrc_t resource)196 static inline int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource)
197 {
198 return -EOPNOTSUPP;
199 }
200
201 /* MISC API */
sc_misc_set_control(sc_ipc_t ipc,sc_rsrc_t resource,sc_ctrl_t ctrl,u32 val)202 static inline int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 val)
203 {
204 return -EOPNOTSUPP;
205 }
206
sc_misc_get_control(sc_ipc_t ipc,sc_rsrc_t resource,sc_ctrl_t ctrl,u32 * val)207 static inline int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 *val)
208 {
209 return -EOPNOTSUPP;
210 }
211
sc_misc_get_boot_dev(sc_ipc_t ipc,sc_rsrc_t * boot_dev)212 static inline void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev)
213 {
214 }
215
sc_misc_boot_status(sc_ipc_t ipc,sc_misc_boot_status_t status)216 static inline void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status)
217 {
218 }
219
sc_misc_get_boot_container(sc_ipc_t ipc,u8 * idx)220 static inline int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx)
221 {
222 return -EOPNOTSUPP;
223 }
224
sc_misc_build_info(sc_ipc_t ipc,u32 * build,u32 * commit)225 static inline void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit)
226 {
227 }
228
sc_misc_otp_fuse_read(sc_ipc_t ipc,u32 word,u32 * val)229 static inline int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val)
230 {
231 return -EOPNOTSUPP;
232 }
233
sc_misc_get_temp(sc_ipc_t ipc,sc_rsrc_t resource,sc_misc_temp_t temp,s16 * celsius,s8 * tenths)234 static inline int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
235 s16 *celsius, s8 *tenths)
236 {
237 return -EOPNOTSUPP;
238 }
239
240 /* RM API */
sc_rm_is_memreg_owned(sc_ipc_t ipc,sc_rm_mr_t mr)241 static inline sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
242 {
243 return true;
244 }
245
sc_rm_find_memreg(sc_ipc_t ipc,sc_rm_mr_t * mr,sc_faddr_t addr_start,sc_faddr_t addr_end)246 static inline int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start,
247 sc_faddr_t addr_end)
248 {
249 return -EOPNOTSUPP;
250 }
251
sc_rm_set_memreg_permissions(sc_ipc_t ipc,sc_rm_mr_t mr,sc_rm_pt_t pt,sc_rm_perm_t perm)252 static inline int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, sc_rm_pt_t pt,
253 sc_rm_perm_t perm)
254 {
255 return -EOPNOTSUPP;
256 }
257
sc_rm_get_memreg_info(sc_ipc_t ipc,sc_rm_mr_t mr,sc_faddr_t * addr_start,sc_faddr_t * addr_end)258 static inline int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start,
259 sc_faddr_t *addr_end)
260 {
261 return -EOPNOTSUPP;
262 }
263
sc_rm_is_resource_owned(sc_ipc_t ipc,sc_rsrc_t resource)264 static inline sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource)
265 {
266 return true;
267 }
268
sc_rm_partition_alloc(sc_ipc_t ipc,sc_rm_pt_t * pt,sc_bool_t secure,sc_bool_t isolated,sc_bool_t restricted,sc_bool_t grant,sc_bool_t coherent)269 static inline int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
270 sc_bool_t isolated, sc_bool_t restricted,
271 sc_bool_t grant, sc_bool_t coherent)
272 {
273 return -EOPNOTSUPP;
274 }
275
sc_rm_partition_free(sc_ipc_t ipc,sc_rm_pt_t pt)276 static inline int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt)
277 {
278 return -EOPNOTSUPP;
279 }
280
sc_rm_get_partition(sc_ipc_t ipc,sc_rm_pt_t * pt)281 static inline int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt)
282 {
283 return -EOPNOTSUPP;
284 }
285
sc_rm_set_parent(sc_ipc_t ipc,sc_rm_pt_t pt,sc_rm_pt_t pt_parent)286 static inline int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent)
287 {
288 return -EOPNOTSUPP;
289 }
290
sc_rm_assign_resource(sc_ipc_t ipc,sc_rm_pt_t pt,sc_rsrc_t resource)291 static inline int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource)
292 {
293 return -EOPNOTSUPP;
294 }
295
sc_rm_assign_pad(sc_ipc_t ipc,sc_rm_pt_t pt,sc_pad_t pad)296 static inline int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad)
297 {
298 return -EOPNOTSUPP;
299 }
300
sc_rm_is_pad_owned(sc_ipc_t ipc,sc_pad_t pad)301 static inline sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad)
302 {
303 return true;
304 }
305
sc_rm_get_resource_owner(sc_ipc_t ipc,sc_rsrc_t resource,sc_rm_pt_t * pt)306 static inline int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_pt_t *pt)
307 {
308 return -EOPNOTSUPP;
309 }
310
311 /* PAD API */
sc_pad_set(sc_ipc_t ipc,sc_pad_t pad,u32 val)312 static inline int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val)
313 {
314 return -EOPNOTSUPP;
315 }
316
sc_pad_get(sc_ipc_t ipc,sc_pad_t pad,uint32_t * val)317 static inline int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val)
318 {
319 return -EOPNOTSUPP;
320 }
321
322 /* SMMU API */
sc_rm_set_master_sid(sc_ipc_t ipc,sc_rsrc_t resource,sc_rm_sid_t sid)323 static inline int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid)
324 {
325 return -EOPNOTSUPP;
326 }
327
328 /* SECO API */
sc_seco_authenticate(sc_ipc_t ipc,sc_seco_auth_cmd_t cmd,sc_faddr_t addr)329 static inline int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr)
330 {
331 return -EOPNOTSUPP;
332 }
333
sc_seco_forward_lifecycle(sc_ipc_t ipc,u32 change)334 static inline int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change)
335 {
336 return -EOPNOTSUPP;
337 }
338
sc_seco_chip_info(sc_ipc_t ipc,u16 * lc,u16 * monotonic,u32 * uid_l,u32 * uid_h)339 static inline int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, u32 *uid_h)
340 {
341 return -EOPNOTSUPP;
342 }
343
sc_seco_build_info(sc_ipc_t ipc,u32 * version,u32 * commit)344 void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit)
345 {
346 }
347
sc_seco_get_event(sc_ipc_t ipc,u8 idx,u32 * event)348 static inline int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event)
349 {
350 return -EOPNOTSUPP;
351 }
352
sc_seco_gen_key_blob(sc_ipc_t ipc,u32 id,sc_faddr_t load_addr,sc_faddr_t export_addr,u16 max_size)353 static inline int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
354 sc_faddr_t export_addr, u16 max_size)
355 {
356 return -EOPNOTSUPP;
357 }
358
sc_seco_get_mp_key(sc_ipc_t ipc,sc_faddr_t dst_addr,u16 dst_size)359 static inline int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size)
360 {
361 return -EOPNOTSUPP;
362 }
363
sc_seco_update_mpmr(sc_ipc_t ipc,sc_faddr_t addr,u8 size,u8 lock)364 static inline int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock)
365 {
366 return -EOPNOTSUPP;
367 }
368
sc_seco_get_mp_sign(sc_ipc_t ipc,sc_faddr_t msg_addr,u16 msg_size,sc_faddr_t dst_addr,u16 dst_size)369 static inline int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, u16 msg_size,
370 sc_faddr_t dst_addr, u16 dst_size)
371 {
372 return -EOPNOTSUPP;
373 }
374
sc_seco_secvio_dgo_config(sc_ipc_t ipc,u8 id,u8 access,u32 * data)375 static inline int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data)
376 {
377 return -EOPNOTSUPP;
378 }
379
sc_seco_secvio_config(sc_ipc_t ipc,u8 id,u8 access,u32 * data0,u32 * data1,u32 * data2,u32 * data3,u32 * data4,u8 size)380 static inline int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data0, u32 *data1,
381 u32 *data2, u32 *data3, u32 *data4, u8 size)
382 {
383 return -EOPNOTSUPP;
384 }
385
sc_pm_reboot(sc_ipc_t ipc,sc_pm_reset_type_t type)386 static inline void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
387 {
388 }
389
sc_pm_reset_reason(sc_ipc_t ipc,sc_pm_reset_reason_t * reason)390 static inline int sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason)
391 {
392 return -EOPNOTSUPP;
393 }
394
sc_seco_v2x_build_info(sc_ipc_t ipc,u32 * version,u32 * commit)395 static inline int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit)
396 {
397 return -EOPNOTSUPP;
398 }
399
sc_misc_get_button_status(sc_ipc_t ipc,sc_bool_t * status)400 static inline void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status)
401 {
402 }
403
sc_timer_set_wdog_window(sc_ipc_t ipc,sc_timer_wdog_time_t window)404 static inline int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window)
405 {
406 return -EOPNOTSUPP;
407 }
408 #endif
409
410 #endif
411