1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2018 NXP 4 */ 5 6 #ifndef SC_PM_API_H 7 #define SC_PM_API_H 8 9 #include <firmware/imx/sci/types.h> 10 /* Defines for type widths */ 11 #define SC_PM_POWER_MODE_W 2U /* Width of sc_pm_power_mode_t */ 12 #define SC_PM_CLOCK_MODE_W 3U /* Width of sc_pm_clock_mode_t */ 13 #define SC_PM_RESET_TYPE_W 2U /* Width of sc_pm_reset_type_t */ 14 #define SC_PM_RESET_REASON_W 4U /* Width of sc_pm_reset_reason_t */ 15 /* Defines for ALL parameters */ 16 #define SC_PM_CLK_ALL ((sc_pm_clk_t)UINT8_MAX) /* All clocks */ 17 /* Defines for sc_pm_power_mode_t */ 18 #define SC_PM_PW_MODE_OFF 0U /* Power off */ 19 #define SC_PM_PW_MODE_STBY 1U /* Power in standby */ 20 #define SC_PM_PW_MODE_LP 2U /* Power in low-power */ 21 #define SC_PM_PW_MODE_ON 3U /* Power on */ 22 23 /* Defines for sc_pm_clk_t */ 24 #define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */ 25 #define SC_PM_CLK_MST_BUS 1U /* Master bus clock */ 26 #define SC_PM_CLK_PER 2U /* Peripheral clock */ 27 #define SC_PM_CLK_PHY 3U /* Phy clock */ 28 #define SC_PM_CLK_MISC 4U /* Misc clock */ 29 #define SC_PM_CLK_MISC0 0U /* Misc 0 clock */ 30 #define SC_PM_CLK_MISC1 1U /* Misc 1 clock */ 31 #define SC_PM_CLK_MISC2 2U /* Misc 2 clock */ 32 #define SC_PM_CLK_MISC3 3U /* Misc 3 clock */ 33 #define SC_PM_CLK_MISC4 4U /* Misc 4 clock */ 34 #define SC_PM_CLK_CPU 2U /* CPU clock */ 35 #define SC_PM_CLK_PLL 4U /* PLL */ 36 #define SC_PM_CLK_BYPASS 4U /* Bypass clock */ 37 38 /* Defines for sc_pm_clk_mode_t */ 39 #define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */ 40 #define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */ 41 #define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */ 42 #define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */ 43 #define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ 44 #define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */ 45 46 /* Defines for sc_pm_clk_parent_t */ 47 #define SC_PM_PARENT_XTAL 0U /*!< Parent is XTAL. */ 48 #define SC_PM_PARENT_PLL0 1U /*!< Parent is PLL0 */ 49 #define SC_PM_PARENT_PLL1 2U /*!< Parent is PLL1 or PLL0/2 */ 50 #define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or PLL0/4 */ 51 #define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass clock. */ 52 53 /* Defines for sc_pm_reset_type_t */ 54 #define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */ 55 #define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */ 56 #define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */ 57 58 /* Defines for sc_pm_reset_reason_t */ 59 #define SC_PM_RESET_REASON_POR 0U /* Power on reset */ 60 #define SC_PM_RESET_REASON_JTAG 1U /* JTAG reset */ 61 #define SC_PM_RESET_REASON_SW 2U /* Software reset */ 62 #define SC_PM_RESET_REASON_WDOG 3U /* Partition watchdog reset */ 63 #define SC_PM_RESET_REASON_LOCKUP 4U /* SCU lockup reset */ 64 #define SC_PM_RESET_REASON_SNVS 5U /* SNVS reset */ 65 #define SC_PM_RESET_REASON_TEMP 6U /* Temp panic reset */ 66 #define SC_PM_RESET_REASON_MSI 7U /* MSI reset */ 67 #define SC_PM_RESET_REASON_UECC 8U /* ECC reset */ 68 #define SC_PM_RESET_REASON_SCFW_WDOG 9U /* SCFW watchdog reset */ 69 #define SC_PM_RESET_REASON_ROM_WDOG 10U /* SCU ROM watchdog reset */ 70 #define SC_PM_RESET_REASON_SECO 11U /* SECO reset */ 71 #define SC_PM_RESET_REASON_SCFW_FAULT 12U /* SCFW fault reset */ 72 73 /* Defines for sc_pm_sys_if_t */ 74 #define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */ 75 #define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */ 76 #define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */ 77 #define SC_PM_SYS_IF_DDR 3U /* DDR memory */ 78 79 /* Defines for sc_pm_wake_src_t */ 80 /* No wake source, used for self-kill */ 81 #define SC_PM_WAKE_SRC_NONE 0U 82 /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */ 83 #define SC_PM_WAKE_SRC_SCU 1U 84 /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */ 85 #define SC_PM_WAKE_SRC_IRQSTEER 2U 86 /* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */ 87 #define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U 88 /* Wakeup from GIC to wake CPU */ 89 #define SC_PM_WAKE_SRC_GIC 4U 90 /* Types */ 91 92 /* 93 * This type is used to declare a power mode. Note resources only use 94 * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only 95 * as system power modes. 96 */ 97 typedef u8 sc_pm_power_mode_t; 98 99 /* 100 * This type is used to declare a clock. 101 */ 102 typedef u8 sc_pm_clk_t; 103 104 /* 105 * This type is used to declare a clock mode. 106 */ 107 typedef u8 sc_pm_clk_mode_t; 108 109 /* 110 * This type is used to declare the clock parent. 111 */ 112 typedef u8 sc_pm_clk_parent_t; 113 114 /* 115 * This type is used to declare clock rates. 116 */ 117 typedef u32 sc_pm_clock_rate_t; 118 119 /* 120 * This type is used to declare a desired reset type. 121 */ 122 typedef u8 sc_pm_reset_type_t; 123 124 /* 125 * This type is used to declare a reason for a reset. 126 */ 127 typedef u8 sc_pm_reset_reason_t; 128 129 /* 130 * This type is used to specify a system-level interface to be power managed. 131 */ 132 typedef u8 sc_pm_sys_if_t; 133 134 /* 135 * This type is used to specify a wake source for CPU resources. 136 */ 137 typedef u8 sc_pm_wake_src_t; 138 #endif /* SC_PM_API_H */ 139