1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef FSL_MMDC_H 7 #define FSL_MMDC_H 8 9 /* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */ 10 #define MPWLGCR_HW_WL_EN (1 << 0) 11 12 /* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */ 13 #define MPPDCMPR2_MPR_COMPARE_EN (1 << 0) 14 15 /* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */ 16 #define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28) 17 18 /* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */ 19 #define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4) 20 21 /* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */ 22 #define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067 23 24 /* MMDC Core Refresh Control Register (MMDC_MDREF) */ 25 #define MDREF_START_REFRESH (1 << 0) 26 27 /* MMDC Core Special Command Register (MDSCR) */ 28 #define CMD_ADDR_MSB_MR_OP(x) (x << 24) 29 #define CMD_ADDR_LSB_MR_ADDR(x) (x << 16) 30 #define MDSCR_DISABLE_CFG_REQ (0 << 15) 31 #define MDSCR_ENABLE_CON_REQ (1 << 15) 32 #define MDSCR_CON_ACK (1 << 14) 33 #define MDSCR_WL_EN (1 << 9) 34 #define CMD_NORMAL (0 << 4) 35 #define CMD_PRECHARGE (1 << 4) 36 #define CMD_AUTO_REFRESH (2 << 4) 37 #define CMD_LOAD_MODE_REG (3 << 4) 38 #define CMD_ZQ_CALIBRATION (4 << 4) 39 #define CMD_PRECHARGE_BANK_OPEN (5 << 4) 40 #define CMD_MRR (6 << 4) 41 #define CMD_BANK_ADDR_0 0x0 42 #define CMD_BANK_ADDR_1 0x1 43 #define CMD_BANK_ADDR_2 0x2 44 #define CMD_BANK_ADDR_3 0x3 45 #define CMD_BANK_ADDR_4 0x4 46 #define CMD_BANK_ADDR_5 0x5 47 #define CMD_BANK_ADDR_6 0x6 48 #define CMD_BANK_ADDR_7 0x7 49 50 /* MMDC Core Control Register (MDCTL) */ 51 #define MDCTL_SDE0 (1 << 31) 52 #define MDCTL_SDE1 (1 << 30) 53 54 /* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */ 55 #define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16) 56 57 /* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */ 58 #define MMDC_MPMUR0_FRC_MSR (1 << 11) 59 60 /* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */ 61 /* default 64 for a quarter cycle delay */ 62 #define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040 63 64 /* MMDC Registers */ 65 struct mmdc_regs { 66 u32 mdctl; 67 u32 mdpdc; 68 u32 mdotc; 69 u32 mdcfg0; 70 u32 mdcfg1; 71 u32 mdcfg2; 72 u32 mdmisc; 73 u32 mdscr; 74 u32 mdref; 75 u32 res1[2]; 76 u32 mdrwd; 77 u32 mdor; 78 u32 mdmrr; 79 u32 mdcfg3lp; 80 u32 mdmr4; 81 u32 mdasp; 82 u32 res2[239]; 83 u32 maarcr; 84 u32 mapsr; 85 u32 maexidr0; 86 u32 maexidr1; 87 u32 madpcr0; 88 u32 madpcr1; 89 u32 madpsr0; 90 u32 madpsr1; 91 u32 madpsr2; 92 u32 madpsr3; 93 u32 madpsr4; 94 u32 madpsr5; 95 u32 masbs0; 96 u32 masbs1; 97 u32 res3[2]; 98 u32 magenp; 99 u32 res4[239]; 100 u32 mpzqhwctrl; 101 u32 mpzqswctrl; 102 u32 mpwlgcr; 103 u32 mpwldectrl0; 104 u32 mpwldectrl1; 105 u32 mpwldlst; 106 u32 mpodtctrl; 107 u32 mprddqby0dl; 108 u32 mprddqby1dl; 109 u32 mprddqby2dl; 110 u32 mprddqby3dl; 111 u32 mpwrdqby0dl; 112 u32 mpwrdqby1dl; 113 u32 mpwrdqby2dl; 114 u32 mpwrdqby3dl; 115 u32 mpdgctrl0; 116 u32 mpdgctrl1; 117 u32 mpdgdlst0; 118 u32 mprddlctl; 119 u32 mprddlst; 120 u32 mpwrdlctl; 121 u32 mpwrdlst; 122 u32 mpsdctrl; 123 u32 mpzqlp2ctl; 124 u32 mprddlhwctl; 125 u32 mpwrdlhwctl; 126 u32 mprddlhwst0; 127 u32 mprddlhwst1; 128 u32 mpwrdlhwst0; 129 u32 mpwrdlhwst1; 130 u32 mpwlhwerr; 131 u32 mpdghwst0; 132 u32 mpdghwst1; 133 u32 mpdghwst2; 134 u32 mpdghwst3; 135 u32 mppdcmpr1; 136 u32 mppdcmpr2; 137 u32 mpswdar0; 138 u32 mpswdrdr0; 139 u32 mpswdrdr1; 140 u32 mpswdrdr2; 141 u32 mpswdrdr3; 142 u32 mpswdrdr4; 143 u32 mpswdrdr5; 144 u32 mpswdrdr6; 145 u32 mpswdrdr7; 146 u32 mpmur0; 147 u32 mpwrcadl; 148 u32 mpdccr; 149 }; 150 151 struct fsl_mmdc_info { 152 u32 mdctl; 153 u32 mdpdc; 154 u32 mdotc; 155 u32 mdcfg0; 156 u32 mdcfg1; 157 u32 mdcfg2; 158 u32 mdmisc; 159 u32 mdref; 160 u32 mdrwd; 161 u32 mdor; 162 u32 mdasp; 163 u32 mpodtctrl; 164 u32 mpzqhwctrl; 165 u32 mprddlctl; 166 }; 167 168 void mmdc_init(const struct fsl_mmdc_info *); 169 170 #endif /* FSL_MMDC_H */ 171