1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2019 Intel Corporation. 4 * 5 * Taken from coreboot intelblocks/nvs.h 6 * Copyright 2019 Google LLC 7 */ 8 9 #ifndef _INTEL_GNVS_H_ 10 #define _INTEL_GNVS_H_ 11 12 #include <linux/bitops.h> 13 /* 14 * The chromeos_acpi portion of ACPI GNVS is assumed to live from offset 15 * 0x100 - 0x1000. When defining acpi_global_nvs, use check_member 16 * to ensure that it is properly aligned: 17 * 18 * check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); 19 */ 20 #define GNVS_CHROMEOS_ACPI_OFFSET 0x100 21 22 enum { 23 BOOT_REASON_OTHER = 0, 24 BOOT_REASON_S3DIAG = 9 25 }; 26 27 enum { 28 CHSW_RECOVERY_X86 = BIT(1), 29 CHSW_RECOVERY_EC = BIT(2), 30 CHSW_DEVELOPER_SWITCH = BIT(5), 31 CHSW_FIRMWARE_WP = BIT(9), 32 }; 33 34 enum { 35 RECOVERY_REASON_NONE = 0, 36 RECOVERY_REASON_ME = 1 37 }; 38 39 enum { 40 ACTIVE_ECFW_RO = 0, 41 ACTIVE_ECFW_RW = 1 42 }; 43 44 enum { 45 BINF_RECOVERY = 0, 46 BINF_RW_A = 1, 47 BINF_RW_B = 2 48 }; 49 50 /** 51 * enum cros_fw_type_t - Used to indicate Chromium OS firmware type 52 * 53 * Chromium OS uses a region of the GNVS starting at offset 0x100 to store 54 * various bits of information, including the type of firmware being booted 55 */ 56 enum cros_fw_type_t { 57 FIRMWARE_TYPE_AUTO_DETECT = -1, 58 FIRMWARE_TYPE_RECOVERY = 0, 59 FIRMWARE_TYPE_NORMAL = 1, 60 FIRMWARE_TYPE_DEVELOPER = 2, 61 FIRMWARE_TYPE_NETBOOT = 3, 62 FIRMWARE_TYPE_LEGACY = 4, 63 }; 64 65 struct __packed chromeos_acpi_gnvs { 66 /* ChromeOS-specific */ 67 u32 boot_reason; /* 00 boot reason */ 68 u32 active_main_fw; /* 04 (0=recovery, 1=A, 2=B) */ 69 u32 activeec_fw; /* 08 (0=RO, 1=RW) */ 70 u16 switches; /* 0c CHSW */ 71 u8 hwid[256]; /* 0e HWID */ 72 u8 fwid[64]; /* 10e FWID */ 73 u8 frid[64]; /* 14e FRID - 275 */ 74 u32 main_fw_type; /* 18e (2 = developer mode) */ 75 u32 recovery_reason; /* 192 recovery reason */ 76 u32 fmap_base; /* 196 fmap base address */ 77 u8 vdat[3072]; /* 19a VDAT space filled by verified boot */ 78 u32 fwid_ptr; /* d9a smbios bios version */ 79 u32 mehh[8]; /* d9e management engine hash */ 80 u32 ramoops_base; /* dbe ramoops base address */ 81 u32 ramoops_len; /* dc2 ramoops length */ 82 u32 vpd_ro_base; /* dc6 pointer to RO_VPD */ 83 u32 vpd_ro_size; /* dca size of RO_VPD */ 84 u32 vpd_rw_base; /* dce pointer to RW_VPD */ 85 u32 vpd_rw_size; /* dd2 size of RW_VPD */ 86 u8 pad[298]; /* dd6-eff */ 87 }; 88 89 struct __packed acpi_global_nvs { 90 /* Miscellaneous */ 91 u8 pcnt; /* 0x00 - Processor Count */ 92 u8 ppcm; /* 0x01 - Max PPC State */ 93 u8 lids; /* 0x02 - LID State */ 94 u8 pwrs; /* 0x03 - AC Power State */ 95 u8 dpte; /* 0x04 - Enable DPTF */ 96 u32 cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ 97 u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ 98 u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */ 99 u64 nhla; /* 0x19 - 0x20 - NHLT Address */ 100 u32 nhll; /* 0x21 - 0x24 - NHLT Length */ 101 u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */ 102 u8 scdp; /* 0x29 - SD_CD GPIO portid */ 103 u8 scdo; /* 0x2a - GPIO pad offset relative to the community */ 104 u8 uior; /* 0x2b - UART debug controller init on S3 resume */ 105 u8 ecps; /* 0x2c - SGX Enabled status */ 106 u64 emna; /* 0x2d - 0x34 EPC base address */ 107 u64 elng; /* 0x35 - 0x3C EPC Length */ 108 u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */ 109 #ifdef CONFIG_CHROMEOS 110 /* ChromeOS-specific (0x100 - 0xfff) */ 111 struct chromeos_acpi_gnvs chromeos; 112 #else 113 u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ 114 #endif 115 }; 116 #ifdef CONFIG_CHROMEOS 117 check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); 118 #else 119 check_member(acpi_global_nvs, unused2, GNVS_CHROMEOS_ACPI_OFFSET); 120 #endif 121 122 #endif /* _INTEL_GNVS_H_ */ 123