1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * QUICC Engine (QE) Internal Memory Map. 4 * The Internal Memory Map for devices with QE on them. This 5 * is the superset of all QE devices (8360, etc.). 6 * 7 * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc. 8 * Author: Shlomi Gridih <gridish@freescale.com> 9 */ 10 11 #ifndef __IMMAP_QE_H__ 12 #define __IMMAP_QE_H__ 13 14 #include <config.h> 15 16 #ifdef CONFIG_MPC83xx 17 #if defined(CONFIG_ARCH_MPC8360) 18 #define QE_MURAM_SIZE 0xc000UL 19 #define MAX_QE_RISC 2 20 #define QE_NUM_OF_SNUM 28 21 #elif defined(CONFIG_ARCH_MPC832X) 22 #define QE_MURAM_SIZE 0x4000UL 23 #define MAX_QE_RISC 1 24 #define QE_NUM_OF_SNUM 28 25 #endif 26 #endif 27 28 #ifdef CONFIG_ARCH_LS1021A 29 #define QE_MURAM_SIZE 0x6000UL 30 #define MAX_QE_RISC 1 31 #define QE_NUM_OF_SNUM 28 32 #endif 33 34 #ifdef CONFIG_PPC 35 #define QE_IMMR_OFFSET 0x00140000 36 #else 37 #define QE_IMMR_OFFSET 0x01400000 38 #endif 39 40 /* QE I-RAM */ 41 typedef struct qe_iram { 42 u32 iadd; /* I-RAM Address Register */ 43 u32 idata; /* I-RAM Data Register */ 44 u8 res0[0x4]; 45 u32 iready; 46 u8 res1[0x70]; 47 } __attribute__ ((packed)) qe_iram_t; 48 49 /* QE Interrupt Controller */ 50 typedef struct qe_ic { 51 u32 qicr; 52 u32 qivec; 53 u32 qripnr; 54 u32 qipnr; 55 u32 qipxcc; 56 u32 qipycc; 57 u32 qipwcc; 58 u32 qipzcc; 59 u32 qimr; 60 u32 qrimr; 61 u32 qicnr; 62 u8 res0[0x4]; 63 u32 qiprta; 64 u32 qiprtb; 65 u8 res1[0x4]; 66 u32 qricr; 67 u8 res2[0x20]; 68 u32 qhivec; 69 u8 res3[0x1C]; 70 } __attribute__ ((packed)) qe_ic_t; 71 72 /* Communications Processor */ 73 typedef struct cp_qe { 74 u32 cecr; /* QE command register */ 75 u32 ceccr; /* QE controller configuration register */ 76 u32 cecdr; /* QE command data register */ 77 u8 res0[0xA]; 78 u16 ceter; /* QE timer event register */ 79 u8 res1[0x2]; 80 u16 cetmr; /* QE timers mask register */ 81 u32 cetscr; /* QE time-stamp timer control register */ 82 u32 cetsr1; /* QE time-stamp register 1 */ 83 u32 cetsr2; /* QE time-stamp register 2 */ 84 u8 res2[0x8]; 85 u32 cevter; /* QE virtual tasks event register */ 86 u32 cevtmr; /* QE virtual tasks mask register */ 87 u16 cercr; /* QE RAM control register */ 88 u8 res3[0x2]; 89 u8 res4[0x24]; 90 u16 ceexe1; /* QE external request 1 event register */ 91 u8 res5[0x2]; 92 u16 ceexm1; /* QE external request 1 mask register */ 93 u8 res6[0x2]; 94 u16 ceexe2; /* QE external request 2 event register */ 95 u8 res7[0x2]; 96 u16 ceexm2; /* QE external request 2 mask register */ 97 u8 res8[0x2]; 98 u16 ceexe3; /* QE external request 3 event register */ 99 u8 res9[0x2]; 100 u16 ceexm3; /* QE external request 3 mask register */ 101 u8 res10[0x2]; 102 u16 ceexe4; /* QE external request 4 event register */ 103 u8 res11[0x2]; 104 u16 ceexm4; /* QE external request 4 mask register */ 105 u8 res12[0x2]; 106 u8 res13[0x280]; 107 } __attribute__ ((packed)) cp_qe_t; 108 109 /* QE Multiplexer */ 110 typedef struct qe_mux { 111 u32 cmxgcr; /* CMX general clock route register */ 112 u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ 113 u32 cmxsi1cr_h; /* CMX SI1 clock route high register */ 114 u32 cmxsi1syr; /* CMX SI1 SYNC route register */ 115 u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ 116 u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ 117 u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ 118 u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ 119 u32 cmxupcr; /* CMX UPC clock route register */ 120 u8 res0[0x1C]; 121 } __attribute__ ((packed)) qe_mux_t; 122 123 /* QE Timers */ 124 typedef struct qe_timers { 125 u8 gtcfr1; /* Timer 1 2 global configuration register */ 126 u8 res0[0x3]; 127 u8 gtcfr2; /* Timer 3 4 global configuration register */ 128 u8 res1[0xB]; 129 u16 gtmdr1; /* Timer 1 mode register */ 130 u16 gtmdr2; /* Timer 2 mode register */ 131 u16 gtrfr1; /* Timer 1 reference register */ 132 u16 gtrfr2; /* Timer 2 reference register */ 133 u16 gtcpr1; /* Timer 1 capture register */ 134 u16 gtcpr2; /* Timer 2 capture register */ 135 u16 gtcnr1; /* Timer 1 counter */ 136 u16 gtcnr2; /* Timer 2 counter */ 137 u16 gtmdr3; /* Timer 3 mode register */ 138 u16 gtmdr4; /* Timer 4 mode register */ 139 u16 gtrfr3; /* Timer 3 reference register */ 140 u16 gtrfr4; /* Timer 4 reference register */ 141 u16 gtcpr3; /* Timer 3 capture register */ 142 u16 gtcpr4; /* Timer 4 capture register */ 143 u16 gtcnr3; /* Timer 3 counter */ 144 u16 gtcnr4; /* Timer 4 counter */ 145 u16 gtevr1; /* Timer 1 event register */ 146 u16 gtevr2; /* Timer 2 event register */ 147 u16 gtevr3; /* Timer 3 event register */ 148 u16 gtevr4; /* Timer 4 event register */ 149 u16 gtps; /* Timer 1 prescale register */ 150 u8 res2[0x46]; 151 } __attribute__ ((packed)) qe_timers_t; 152 153 /* BRG */ 154 typedef struct qe_brg { 155 u32 brgc1; /* BRG1 configuration register */ 156 u32 brgc2; /* BRG2 configuration register */ 157 u32 brgc3; /* BRG3 configuration register */ 158 u32 brgc4; /* BRG4 configuration register */ 159 u32 brgc5; /* BRG5 configuration register */ 160 u32 brgc6; /* BRG6 configuration register */ 161 u32 brgc7; /* BRG7 configuration register */ 162 u32 brgc8; /* BRG8 configuration register */ 163 u32 brgc9; /* BRG9 configuration register */ 164 u32 brgc10; /* BRG10 configuration register */ 165 u32 brgc11; /* BRG11 configuration register */ 166 u32 brgc12; /* BRG12 configuration register */ 167 u32 brgc13; /* BRG13 configuration register */ 168 u32 brgc14; /* BRG14 configuration register */ 169 u32 brgc15; /* BRG15 configuration register */ 170 u32 brgc16; /* BRG16 configuration register */ 171 u8 res0[0x40]; 172 } __attribute__ ((packed)) qe_brg_t; 173 174 /* SPI */ 175 typedef struct spi { 176 u8 res0[0x20]; 177 u32 spmode; /* SPI mode register */ 178 u8 res1[0x2]; 179 u8 spie; /* SPI event register */ 180 u8 res2[0x1]; 181 u8 res3[0x2]; 182 u8 spim; /* SPI mask register */ 183 u8 res4[0x1]; 184 u8 res5[0x1]; 185 u8 spcom; /* SPI command register */ 186 u8 res6[0x2]; 187 u32 spitd; /* SPI transmit data register (cpu mode) */ 188 u32 spird; /* SPI receive data register (cpu mode) */ 189 u8 res7[0x8]; 190 } __attribute__ ((packed)) spi_t; 191 192 /* SI */ 193 typedef struct si1 { 194 u16 siamr1; /* SI1 TDMA mode register */ 195 u16 sibmr1; /* SI1 TDMB mode register */ 196 u16 sicmr1; /* SI1 TDMC mode register */ 197 u16 sidmr1; /* SI1 TDMD mode register */ 198 u8 siglmr1_h; /* SI1 global mode register high */ 199 u8 res0[0x1]; 200 u8 sicmdr1_h; /* SI1 command register high */ 201 u8 res2[0x1]; 202 u8 sistr1_h; /* SI1 status register high */ 203 u8 res3[0x1]; 204 u16 sirsr1_h; /* SI1 RAM shadow address register high */ 205 u8 sitarc1; /* SI1 RAM counter Tx TDMA */ 206 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ 207 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ 208 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ 209 u8 sirarc1; /* SI1 RAM counter Rx TDMA */ 210 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ 211 u8 sircrc1; /* SI1 RAM counter Rx TDMC */ 212 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ 213 u8 res4[0x8]; 214 u16 siemr1; /* SI1 TDME mode register 16 bits */ 215 u16 sifmr1; /* SI1 TDMF mode register 16 bits */ 216 u16 sigmr1; /* SI1 TDMG mode register 16 bits */ 217 u16 sihmr1; /* SI1 TDMH mode register 16 bits */ 218 u8 siglmg1_l; /* SI1 global mode register low 8 bits */ 219 u8 res5[0x1]; 220 u8 sicmdr1_l; /* SI1 command register low 8 bits */ 221 u8 res6[0x1]; 222 u8 sistr1_l; /* SI1 status register low 8 bits */ 223 u8 res7[0x1]; 224 u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */ 225 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ 226 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ 227 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ 228 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ 229 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ 230 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ 231 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ 232 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ 233 u8 res8[0x8]; 234 u32 siml1; /* SI1 multiframe limit register */ 235 u8 siedm1; /* SI1 extended diagnostic mode register */ 236 u8 res9[0xBB]; 237 } __attribute__ ((packed)) si1_t; 238 239 /* SI Routing Tables */ 240 typedef struct sir { 241 u8 tx[0x400]; 242 u8 rx[0x400]; 243 u8 res0[0x800]; 244 } __attribute__ ((packed)) sir_t; 245 246 /* USB Controller. */ 247 typedef struct usb_ctlr { 248 u8 usb_usmod; 249 u8 usb_usadr; 250 u8 usb_uscom; 251 u8 res1[1]; 252 u16 usb_usep1; 253 u16 usb_usep2; 254 u16 usb_usep3; 255 u16 usb_usep4; 256 u8 res2[4]; 257 u16 usb_usber; 258 u8 res3[2]; 259 u16 usb_usbmr; 260 u8 res4[1]; 261 u8 usb_usbs; 262 u16 usb_ussft; 263 u8 res5[2]; 264 u16 usb_usfrn; 265 u8 res6[0x22]; 266 } __attribute__ ((packed)) usb_t; 267 268 /* MCC */ 269 typedef struct mcc { 270 u32 mcce; /* MCC event register */ 271 u32 mccm; /* MCC mask register */ 272 u32 mccf; /* MCC configuration register */ 273 u32 merl; /* MCC emergency request level register */ 274 u8 res0[0xF0]; 275 } __attribute__ ((packed)) mcc_t; 276 277 /* QE UCC Slow */ 278 typedef struct ucc_slow { 279 u32 gumr_l; /* UCCx general mode register (low) */ 280 u32 gumr_h; /* UCCx general mode register (high) */ 281 u16 upsmr; /* UCCx protocol-specific mode register */ 282 u8 res0[0x2]; 283 u16 utodr; /* UCCx transmit on demand register */ 284 u16 udsr; /* UCCx data synchronization register */ 285 u16 ucce; /* UCCx event register */ 286 u8 res1[0x2]; 287 u16 uccm; /* UCCx mask register */ 288 u8 res2[0x1]; 289 u8 uccs; /* UCCx status register */ 290 u8 res3[0x24]; 291 u16 utpt; 292 u8 guemr; /* UCC general extended mode register */ 293 u8 res4[0x200 - 0x091]; 294 } __attribute__ ((packed)) ucc_slow_t; 295 296 typedef struct ucc_mii_mng { 297 u32 miimcfg; /* MII management configuration reg */ 298 u32 miimcom; /* MII management command reg */ 299 u32 miimadd; /* MII management address reg */ 300 u32 miimcon; /* MII management control reg */ 301 u32 miimstat; /* MII management status reg */ 302 u32 miimind; /* MII management indication reg */ 303 u32 ifctl; /* interface control reg */ 304 u32 ifstat; /* interface statux reg */ 305 } __attribute__ ((packed))uec_mii_t; 306 307 typedef struct ucc_ethernet { 308 u32 maccfg1; /* mac configuration reg. 1 */ 309 u32 maccfg2; /* mac configuration reg. 2 */ 310 u32 ipgifg; /* interframe gap reg. */ 311 u32 hafdup; /* half-duplex reg. */ 312 u8 res1[0x10]; 313 u32 miimcfg; /* MII management configuration reg */ 314 u32 miimcom; /* MII management command reg */ 315 u32 miimadd; /* MII management address reg */ 316 u32 miimcon; /* MII management control reg */ 317 u32 miimstat; /* MII management status reg */ 318 u32 miimind; /* MII management indication reg */ 319 u32 ifctl; /* interface control reg */ 320 u32 ifstat; /* interface statux reg */ 321 u32 macstnaddr1; /* mac station address part 1 reg */ 322 u32 macstnaddr2; /* mac station address part 2 reg */ 323 u8 res2[0x8]; 324 u32 uempr; /* UCC Ethernet Mac parameter reg */ 325 u32 utbipar; /* UCC tbi address reg */ 326 u16 uescr; /* UCC Ethernet statistics control reg */ 327 u8 res3[0x180 - 0x15A]; 328 u32 tx64; /* Total number of frames (including bad 329 * frames) transmitted that were exactly 330 * of the minimal length (64 for un tagged, 331 * 68 for tagged, or with length exactly 332 * equal to the parameter MINLength */ 333 u32 tx127; /* Total number of frames (including bad 334 * frames) transmitted that were between 335 * MINLength (Including FCS length==4) 336 * and 127 octets */ 337 u32 tx255; /* Total number of frames (including bad 338 * frames) transmitted that were between 339 * 128 (Including FCS length==4) and 255 340 * octets */ 341 u32 rx64; /* Total number of frames received including 342 * bad frames that were exactly of the 343 * mninimal length (64 bytes) */ 344 u32 rx127; /* Total number of frames (including bad 345 * frames) received that were between 346 * MINLength (Including FCS length==4) 347 * and 127 octets */ 348 u32 rx255; /* Total number of frames (including 349 * bad frames) received that were between 350 * 128 (Including FCS length==4) and 255 351 * octets */ 352 u32 txok; /* Total number of octets residing in frames 353 * that where involved in succesfull 354 * transmission */ 355 u16 txcf; /* Total number of PAUSE control frames 356 * transmitted by this MAC */ 357 u8 res4[0x2]; 358 u32 tmca; /* Total number of frames that were transmitted 359 * succesfully with the group address bit set 360 * that are not broadcast frames */ 361 u32 tbca; /* Total number of frames transmitted 362 * succesfully that had destination address 363 * field equal to the broadcast address */ 364 u32 rxfok; /* Total number of frames received OK */ 365 u32 rxbok; /* Total number of octets received OK */ 366 u32 rbyt; /* Total number of octets received including 367 * octets in bad frames. Must be implemented 368 * in HW because it includes octets in frames 369 * that never even reach the UCC */ 370 u32 rmca; /* Total number of frames that were received 371 * succesfully with the group address bit set 372 * that are not broadcast frames */ 373 u32 rbca; /* Total number of frames received succesfully 374 * that had destination address equal to the 375 * broadcast address */ 376 u32 scar; /* Statistics carry register */ 377 u32 scam; /* Statistics caryy mask register */ 378 u8 res5[0x200 - 0x1c4]; 379 } __attribute__ ((packed)) uec_t; 380 381 /* QE UCC Fast */ 382 typedef struct ucc_fast { 383 u32 gumr; /* UCCx general mode register */ 384 u32 upsmr; /* UCCx protocol-specific mode register */ 385 u16 utodr; /* UCCx transmit on demand register */ 386 u8 res0[0x2]; 387 u16 udsr; /* UCCx data synchronization register */ 388 u8 res1[0x2]; 389 u32 ucce; /* UCCx event register */ 390 u32 uccm; /* UCCx mask register. */ 391 u8 uccs; /* UCCx status register */ 392 u8 res2[0x7]; 393 u32 urfb; /* UCC receive FIFO base */ 394 u16 urfs; /* UCC receive FIFO size */ 395 u8 res3[0x2]; 396 u16 urfet; /* UCC receive FIFO emergency threshold */ 397 u16 urfset; /* UCC receive FIFO special emergency 398 * threshold */ 399 u32 utfb; /* UCC transmit FIFO base */ 400 u16 utfs; /* UCC transmit FIFO size */ 401 u8 res4[0x2]; 402 u16 utfet; /* UCC transmit FIFO emergency threshold */ 403 u8 res5[0x2]; 404 u16 utftt; /* UCC transmit FIFO transmit threshold */ 405 u8 res6[0x2]; 406 u16 utpt; /* UCC transmit polling timer */ 407 u8 res7[0x2]; 408 u32 urtry; /* UCC retry counter register */ 409 u8 res8[0x4C]; 410 u8 guemr; /* UCC general extended mode register */ 411 u8 res9[0x100 - 0x091]; 412 uec_t ucc_eth; 413 } __attribute__ ((packed)) ucc_fast_t; 414 415 /* QE UCC */ 416 typedef struct ucc_common { 417 u8 res1[0x90]; 418 u8 guemr; 419 u8 res2[0x200 - 0x091]; 420 } __attribute__ ((packed)) ucc_common_t; 421 422 typedef struct ucc { 423 union { 424 ucc_slow_t slow; 425 ucc_fast_t fast; 426 ucc_common_t common; 427 }; 428 } __attribute__ ((packed)) ucc_t; 429 430 /* MultiPHY UTOPIA POS Controllers (UPC) */ 431 typedef struct upc { 432 u32 upgcr; /* UTOPIA/POS general configuration register */ 433 u32 uplpa; /* UTOPIA/POS last PHY address */ 434 u32 uphec; /* ATM HEC register */ 435 u32 upuc; /* UTOPIA/POS UCC configuration */ 436 u32 updc1; /* UTOPIA/POS device 1 configuration */ 437 u32 updc2; /* UTOPIA/POS device 2 configuration */ 438 u32 updc3; /* UTOPIA/POS device 3 configuration */ 439 u32 updc4; /* UTOPIA/POS device 4 configuration */ 440 u32 upstpa; /* UTOPIA/POS STPA threshold */ 441 u8 res0[0xC]; 442 u32 updrs1_h; /* UTOPIA/POS device 1 rate select */ 443 u32 updrs1_l; /* UTOPIA/POS device 1 rate select */ 444 u32 updrs2_h; /* UTOPIA/POS device 2 rate select */ 445 u32 updrs2_l; /* UTOPIA/POS device 2 rate select */ 446 u32 updrs3_h; /* UTOPIA/POS device 3 rate select */ 447 u32 updrs3_l; /* UTOPIA/POS device 3 rate select */ 448 u32 updrs4_h; /* UTOPIA/POS device 4 rate select */ 449 u32 updrs4_l; /* UTOPIA/POS device 4 rate select */ 450 u32 updrp1; /* UTOPIA/POS device 1 receive priority low */ 451 u32 updrp2; /* UTOPIA/POS device 2 receive priority low */ 452 u32 updrp3; /* UTOPIA/POS device 3 receive priority low */ 453 u32 updrp4; /* UTOPIA/POS device 4 receive priority low */ 454 u32 upde1; /* UTOPIA/POS device 1 event */ 455 u32 upde2; /* UTOPIA/POS device 2 event */ 456 u32 upde3; /* UTOPIA/POS device 3 event */ 457 u32 upde4; /* UTOPIA/POS device 4 event */ 458 u16 uprp1; 459 u16 uprp2; 460 u16 uprp3; 461 u16 uprp4; 462 u8 res1[0x8]; 463 u16 uptirr1_0; /* Device 1 transmit internal rate 0 */ 464 u16 uptirr1_1; /* Device 1 transmit internal rate 1 */ 465 u16 uptirr1_2; /* Device 1 transmit internal rate 2 */ 466 u16 uptirr1_3; /* Device 1 transmit internal rate 3 */ 467 u16 uptirr2_0; /* Device 2 transmit internal rate 0 */ 468 u16 uptirr2_1; /* Device 2 transmit internal rate 1 */ 469 u16 uptirr2_2; /* Device 2 transmit internal rate 2 */ 470 u16 uptirr2_3; /* Device 2 transmit internal rate 3 */ 471 u16 uptirr3_0; /* Device 3 transmit internal rate 0 */ 472 u16 uptirr3_1; /* Device 3 transmit internal rate 1 */ 473 u16 uptirr3_2; /* Device 3 transmit internal rate 2 */ 474 u16 uptirr3_3; /* Device 3 transmit internal rate 3 */ 475 u16 uptirr4_0; /* Device 4 transmit internal rate 0 */ 476 u16 uptirr4_1; /* Device 4 transmit internal rate 1 */ 477 u16 uptirr4_2; /* Device 4 transmit internal rate 2 */ 478 u16 uptirr4_3; /* Device 4 transmit internal rate 3 */ 479 u32 uper1; /* Device 1 port enable register */ 480 u32 uper2; /* Device 2 port enable register */ 481 u32 uper3; /* Device 3 port enable register */ 482 u32 uper4; /* Device 4 port enable register */ 483 u8 res2[0x150]; 484 } __attribute__ ((packed)) upc_t; 485 486 /* SDMA */ 487 typedef struct sdma { 488 u32 sdsr; /* Serial DMA status register */ 489 u32 sdmr; /* Serial DMA mode register */ 490 u32 sdtr1; /* SDMA system bus threshold register */ 491 u32 sdtr2; /* SDMA secondary bus threshold register */ 492 u32 sdhy1; /* SDMA system bus hysteresis register */ 493 u32 sdhy2; /* SDMA secondary bus hysteresis register */ 494 u32 sdta1; /* SDMA system bus address register */ 495 u32 sdta2; /* SDMA secondary bus address register */ 496 u32 sdtm1; /* SDMA system bus MSNUM register */ 497 u32 sdtm2; /* SDMA secondary bus MSNUM register */ 498 u8 res0[0x10]; 499 u32 sdaqr; /* SDMA address bus qualify register */ 500 u32 sdaqmr; /* SDMA address bus qualify mask register */ 501 u8 res1[0x4]; 502 u32 sdwbcr; /* SDMA CAM entries base register */ 503 u8 res2[0x38]; 504 } __attribute__ ((packed)) sdma_t; 505 506 /* Debug Space */ 507 typedef struct dbg { 508 u32 bpdcr; /* Breakpoint debug command register */ 509 u32 bpdsr; /* Breakpoint debug status register */ 510 u32 bpdmr; /* Breakpoint debug mask register */ 511 u32 bprmrr0; /* Breakpoint request mode risc register 0 */ 512 u32 bprmrr1; /* Breakpoint request mode risc register 1 */ 513 u8 res0[0x8]; 514 u32 bprmtr0; /* Breakpoint request mode trb register 0 */ 515 u32 bprmtr1; /* Breakpoint request mode trb register 1 */ 516 u8 res1[0x8]; 517 u32 bprmir; /* Breakpoint request mode immediate register */ 518 u32 bprmsr; /* Breakpoint request mode serial register */ 519 u32 bpemr; /* Breakpoint exit mode register */ 520 u8 res2[0x48]; 521 } __attribute__ ((packed)) dbg_t; 522 523 /* 524 * RISC Special Registers (Trap and Breakpoint). These are described in 525 * the QE Developer's Handbook. 526 */ 527 typedef struct rsp { 528 u32 tibcr[16]; /* Trap/instruction breakpoint control regs */ 529 u8 res0[64]; 530 u32 ibcr0; 531 u32 ibs0; 532 u32 ibcnr0; 533 u8 res1[4]; 534 u32 ibcr1; 535 u32 ibs1; 536 u32 ibcnr1; 537 u32 npcr; 538 u32 dbcr; 539 u32 dbar; 540 u32 dbamr; 541 u32 dbsr; 542 u32 dbcnr; 543 u8 res2[12]; 544 u32 dbdr_h; 545 u32 dbdr_l; 546 u32 dbdmr_h; 547 u32 dbdmr_l; 548 u32 bsr; 549 u32 bor; 550 u32 bior; 551 u8 res3[4]; 552 u32 iatr[4]; 553 u32 eccr; /* Exception control configuration register */ 554 u32 eicr; 555 u8 res4[0x100-0xf8]; 556 } __attribute__ ((packed)) rsp_t; 557 558 typedef struct qe_immap { 559 qe_iram_t iram; /* I-RAM */ 560 qe_ic_t ic; /* Interrupt Controller */ 561 cp_qe_t cp; /* Communications Processor */ 562 qe_mux_t qmx; /* QE Multiplexer */ 563 qe_timers_t qet; /* QE Timers */ 564 spi_t spi[0x2]; /* spi */ 565 mcc_t mcc; /* mcc */ 566 qe_brg_t brg; /* brg */ 567 usb_t usb; /* USB */ 568 si1_t si1; /* SI */ 569 u8 res11[0x800]; 570 sir_t sir; /* SI Routing Tables */ 571 ucc_t ucc1; /* ucc1 */ 572 ucc_t ucc3; /* ucc3 */ 573 ucc_t ucc5; /* ucc5 */ 574 ucc_t ucc7; /* ucc7 */ 575 u8 res12[0x600]; 576 upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */ 577 ucc_t ucc2; /* ucc2 */ 578 ucc_t ucc4; /* ucc4 */ 579 ucc_t ucc6; /* ucc6 */ 580 ucc_t ucc8; /* ucc8 */ 581 u8 res13[0x600]; 582 upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */ 583 sdma_t sdma; /* SDMA */ 584 dbg_t dbg; /* Debug Space */ 585 rsp_t rsp[0x2]; /* RISC Special Registers 586 * (Trap and Breakpoint) */ 587 u8 res14[0x300]; 588 u8 res15[0x3A00]; 589 u8 res16[0x8000]; /* 0x108000 - 0x110000 */ 590 u8 muram[QE_MURAM_SIZE]; 591 } __attribute__ ((packed)) qe_map_t; 592 593 extern qe_map_t *qe_immr; 594 595 #endif /* __IMMAP_QE_H__ */ 596