1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2017-2018, Intel Corporation 4 * Copyright (C) 2025 Altera Corporation <www.altera.com> 5 */ 6 7 #ifndef __INTEL_SMC_H 8 #define __INTEL_SMC_H 9 10 #include <linux/arm-smccc.h> 11 #include <linux/bitops.h> 12 13 /* 14 * This file defines the Secure Monitor Call (SMC) message protocol used for 15 * service layer driver in normal world (EL1) to communicate with secure 16 * monitor software in Secure Monitor Exception Level 3 (EL3). 17 * 18 * This file is shared with secure firmware (FW) which is out of u-boot tree. 19 * 20 * An ARM SMC instruction takes a function identifier and up to 6 64-bit 21 * register values as arguments, and can return up to 4 64-bit register 22 * values. The operation of the secure monitor is determined by the parameter 23 * values passed in through registers. 24 25 * EL1 and EL3 communicates pointer as physical address rather than the 26 * virtual address. 27 */ 28 29 /* 30 * Functions specified by ARM SMC Calling convention: 31 * 32 * FAST call executes atomic operations, returns when the requested operation 33 * has completed. 34 * STD call starts a operation which can be preempted by a non-secure 35 * interrupt. The call can return before the requested operation has 36 * completed. 37 * 38 * a0..a7 is used as register names in the descriptions below, on arm32 39 * that translates to r0..r7 and on arm64 to w0..w7. 40 */ 41 42 #define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ 43 ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ 44 ARM_SMCCC_OWNER_SIP, (func_num)) 45 46 #define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ 47 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ 48 ARM_SMCCC_OWNER_SIP, (func_num)) 49 50 /* 51 * Return values in INTEL_SIP_SMC_* call 52 * 53 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: 54 * Secure monitor software doesn't recognize the request. 55 * 56 * INTEL_SIP_SMC_STATUS_OK: 57 * SMC call completed successfully, 58 * In case of FPGA configuration write operation, it means secure monitor 59 * software can accept the next chunk of FPGA configuration data. 60 * 61 * INTEL_SIP_SMC_STATUS_BUSY: 62 * In case of FPGA configuration write operation, it means secure monitor 63 * software is still processing previous data & can't accept the next chunk 64 * of data. Service driver needs to issue 65 * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the 66 * completed block(s). 67 * 68 * INTEL_SIP_SMC_STATUS_ERROR: 69 * There is error during the SMC call process. 70 * 71 * INTEL_SIP_SMC_REG_ERROR: 72 * There is error during a read or write operation of the protected 73 * registers. 74 */ 75 #define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF 76 #define INTEL_SIP_SMC_STATUS_OK 0x0 77 #define INTEL_SIP_SMC_STATUS_BUSY 0x1 78 #define INTEL_SIP_SMC_STATUS_REJECTED 0x2 79 #define INTEL_SIP_SMC_STATUS_ERROR 0x4 80 #define INTEL_SIP_SMC_REG_ERROR 0x5 81 #define INTEL_SIP_SMC_RSU_ERROR 0x7 82 83 /* 84 * Request INTEL_SIP_SMC_FPGA_CONFIG_START 85 * 86 * Sync call used by service driver at EL1 to request the FPGA in EL3 to 87 * be prepare to receive a new configuration. 88 * 89 * Call register usage: 90 * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. 91 * a1: flag for full or partial configuration 92 * 0 full reconfiguration. 93 * 1 partial reconfiguration. 94 * a2-7: not used. 95 * 96 * Return status: 97 * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. 98 * a1-3: not used. 99 */ 100 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 101 #define INTEL_SIP_SMC_FPGA_CONFIG_START \ 102 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) 103 104 /* 105 * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE 106 * 107 * Async call used by service driver at EL1 to provide FPGA configuration data 108 * to secure world. 109 * 110 * Call register usage: 111 * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. 112 * a1: 64bit physical address of the configuration data memory block 113 * a2: Size of configuration data block. 114 * a3-7: not used. 115 * 116 * Return status: 117 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY, 118 * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR. 119 * a1: 64bit physical address of 1st completed memory block if any completed 120 * block, otherwise zero value. 121 * a2: 64bit physical address of 2nd completed memory block if any completed 122 * block, otherwise zero value. 123 * a3: 64bit physical address of 3rd completed memory block if any completed 124 * block, otherwise zero value. 125 */ 126 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2 127 #define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \ 128 INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE) 129 130 /* 131 * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 132 * 133 * Sync call used by service driver at EL1 to track the completed write 134 * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE 135 * call returns INTEL_SIP_SMC_STATUS_BUSY. 136 * 137 * Call register usage: 138 * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE. 139 * a1-7: not used. 140 * 141 * Return status: 142 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or 143 * INTEL_SIP_SMC_STATUS_ERROR. 144 * a1: 64bit physical address of 1st completed memory block. 145 * a2: 64bit physical address of 2nd completed memory block if 146 * any completed block, otherwise zero value. 147 * a3: 64bit physical address of 3rd completed memory block if 148 * any completed block, otherwise zero value. 149 */ 150 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3 151 #define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \ 152 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) 153 154 /* 155 * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 156 * 157 * Sync call used by service driver at EL1 to inform secure world that all 158 * data are sent, to check whether or not the secure world had completed 159 * the FPGA configuration process. 160 * 161 * Call register usage: 162 * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE. 163 * a1-7: not used. 164 * 165 * Return status: 166 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or 167 * INTEL_SIP_SMC_STATUS_ERROR. 168 * a1-3: not used. 169 */ 170 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4 171 #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \ 172 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE) 173 174 /* 175 * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 176 * 177 * Sync call used by service driver at EL1 to query the physical address of 178 * memory block reserved by secure monitor software. 179 * 180 * Call register usage: 181 * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM. 182 * a1-7: not used. 183 * 184 * Return status: 185 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. 186 * a1: start of physical address of reserved memory block. 187 * a2: size of reserved memory block. 188 * a3: not used. 189 */ 190 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5 191 #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \ 192 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM) 193 194 /* 195 * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK 196 * 197 * For SMC loop-back mode only, used for internal integration, debugging 198 * or troubleshooting. 199 * 200 * Call register usage: 201 * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK. 202 * a1-7: not used. 203 * 204 * Return status: 205 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. 206 * a1-3: not used. 207 */ 208 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6 209 #define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \ 210 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK) 211 212 /* 213 * Request INTEL_SIP_SMC_REG_READ 214 * 215 * Read a protected register using SMCCC 216 * 217 * Call register usage: 218 * a0: INTEL_SIP_SMC_REG_READ. 219 * a1: register address. 220 * a2-7: not used. 221 * 222 * Return status: 223 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. 224 * a1: Value in the register 225 * a2-3: not used. 226 */ 227 #define INTEL_SIP_SMC_FUNCID_REG_READ 7 228 #define INTEL_SIP_SMC_REG_READ \ 229 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ) 230 231 /* 232 * Request INTEL_SIP_SMC_REG_WRITE 233 * 234 * Write a protected register using SMCCC 235 * 236 * Call register usage: 237 * a0: INTEL_SIP_SMC_REG_WRITE. 238 * a1: register address 239 * a2: value to program into register. 240 * a3-7: not used. 241 * 242 * Return status: 243 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. 244 * a1-3: not used. 245 */ 246 #define INTEL_SIP_SMC_FUNCID_REG_WRITE 8 247 #define INTEL_SIP_SMC_REG_WRITE \ 248 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE) 249 250 /* 251 * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE 252 * 253 * Update one or more bits in a protected register using a 254 * read-modify-write operation. 255 * 256 * Call register usage: 257 * a0: INTEL_SIP_SMC_REG_UPDATE. 258 * a1: register address 259 * a2: Write Mask. 260 * a3: Value to write. 261 * a4-7: not used. 262 * 263 * Return status: 264 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. 265 * a1-3: Not used. 266 */ 267 #define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9 268 #define INTEL_SIP_SMC_REG_UPDATE \ 269 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE) 270 271 /* 272 * Request INTEL_SIP_SMC_RSU_STATUS 273 * 274 * Sync call used by service driver at EL1 to query the RSU status 275 * 276 * Call register usage: 277 * a0 INTEL_SIP_SMC_RSU_STATUS 278 * a1-7 not used 279 * 280 * Return status 281 * a0: Current Image 282 * a1: Last Failing Image 283 * a2: Version [width 32 bit] | State [width 32 bit] 284 * a3: Error details [width 32 bit] | Error location [width 32 bit] 285 * 286 * Or 287 * 288 * a0: INTEL_SIP_SMC_RSU_ERROR 289 */ 290 #define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11 291 #define INTEL_SIP_SMC_RSU_STATUS \ 292 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS) 293 294 /* 295 * Request INTEL_SIP_SMC_RSU_UPDATE 296 * 297 * Sync call used by service driver at EL1 to tell you next reboot is RSU_UPDATE 298 * 299 * Call register usage: 300 * a0 INTEL_SIP_SMC_RSU_UPDATE 301 * a1 64bit physical address of the configuration data memory in flash 302 * a2-7 not used 303 * 304 * Return status 305 * a0 INTEL_SIP_SMC_STATUS_OK 306 */ 307 #define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12 308 #define INTEL_SIP_SMC_RSU_UPDATE \ 309 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE) 310 311 /* 312 * Request INTEL_SIP_SMC_ECC_DBE 313 * 314 * Sync call used by service driver at EL1 alert EL3 that a Double Bit 315 * ECC error has occurred. 316 * 317 * Call register usage: 318 * a0 INTEL_SIP_SMC_ECC_DBE 319 * a1 SysManager Double Bit Error value 320 * a2-7 not used 321 * 322 * Return status 323 * a0 INTEL_SIP_SMC_STATUS_OK 324 */ 325 #define INTEL_SIP_SMC_FUNCID_ECC_DBE 13 326 #define INTEL_SIP_SMC_ECC_DBE \ 327 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE) 328 329 /* 330 * Request INTEL_SIP_SMC_RSU_NOTIFY 331 * 332 * Sync call used by service driver at EL1 to report HPS software execution stage 333 * 334 * Call register usage: 335 * a0 INTEL_SIP_SMC_RSU_NOTIFY 336 * a1 32bit HPS software execution stage 337 * a2-7 not used 338 * 339 * Return status 340 * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. 341 */ 342 #define INTEL_SIP_SMC_FUNCID_RSU_NOTIFY 14 343 #define INTEL_SIP_SMC_RSU_NOTIFY \ 344 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_NOTIFY) 345 346 /* 347 * Request INTEL_SIP_SMC_RSU_RETRY_COUNTER 348 * 349 * Sync call used by service driver at EL1 to query the RSU retry counter 350 * 351 * Call register usage: 352 * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER 353 * a1-7 not used 354 * 355 * Return status 356 * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_RSU_ERROR. 357 * a1 retry counter 358 */ 359 #define INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER 15 360 #define INTEL_SIP_SMC_RSU_RETRY_COUNTER \ 361 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER) 362 363 /* 364 * Request INTEL_SIP_SMC_RSU_DCMF_VERSION 365 * 366 * Sync call used by service driver at EL1 to query DCMF version 367 * 368 * Call register usage: 369 * a0 INTEL_SIP_SMC_RSU_DCMF_VERSION 370 * a1-7 not used 371 * 372 * Return status 373 * a0 INTEL_SIP_SMC_STATUS_OK 374 * a1 dcmf1 version | dcmf0 version 375 * a2 dcmf3 version | dcmf2 version 376 * 377 * Or 378 * 379 * a0 INTEL_SIP_SMC_RSU_ERROR 380 */ 381 #define INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION 16 382 #define INTEL_SIP_SMC_RSU_DCMF_VERSION \ 383 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION) 384 385 /* 386 * Request INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 387 * 388 * Sync call used by SSBL (EL2) to copy DCMF version to ATF memory 389 * 390 * Call register usage: 391 * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 392 * a1 dcmf1 version | dcmf0 version 393 * a2 dcmf3 version | dcmf2 version 394 * 395 * Return status 396 * a0 INTEL_SIP_SMC_STATUS_OK 397 */ 398 #define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION 17 399 #define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION \ 400 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION) 401 402 /* 403 * Request INTEL_SIP_SMC_RSU_MAX_RETRY 404 * 405 * Sync call used by service driver at EL1 to query max_retry parameter 406 * 407 * Call register usage: 408 * a0 INTEL_SIP_SMC_RSU_MAX_RETRY 409 * a1-7 not used 410 * 411 * Return status 412 * a0 INTEL_SIP_SMC_STATUS_OK 413 * a1 max_retry 414 * 415 * Or 416 * 417 * a0 INTEL_SIP_SMC_RSU_ERROR 418 */ 419 #define INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY 18 420 #define INTEL_SIP_SMC_RSU_MAX_RETRY \ 421 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY) 422 423 /* 424 * Request INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 425 * 426 * Sync call used by SSBL (EL2) to copy RSU 'max retry' to ATF memory 427 * 428 * Call register usage: 429 * a0 INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 430 * a1 max retry 431 * a2-7 not used 432 * 433 * Return status 434 * a0 INTEL_SIP_SMC_STATUS_OK 435 */ 436 #define INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY 19 437 #define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY \ 438 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY) 439 440 /* 441 * Request INTEL_SIP_SMC_RSU_DCMF_STATUS 442 * 443 * Sync call used by service driver at EL1 to query DCMF status 444 * 445 * Call register usage: 446 * a0 INTEL_SIP_SMC_RSU_DCMF_STATUS 447 * a1-7 not used 448 * 449 * Return status 450 * a0 INTEL_SIP_SMC_STATUS_OK 451 * a1 dcmf3 status | dcmf2 status | dcmf1 status | dcmf0 status 452 * 453 * Or 454 * 455 * a0 INTEL_SIP_SMC_RSU_ERROR 456 */ 457 #define INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS 20 458 #define INTEL_SIP_SMC_RSU_DCMF_STATUS \ 459 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS) 460 461 /* 462 * Request INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 463 * 464 * Sync call used by SSBL (EL2) to copy RSU 'dcmf status' to ATF memory 465 * 466 * Call register usage: 467 * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 468 * a1 dcmf status 469 * a2-7 not used 470 * 471 * Return status 472 * a0 INTEL_SIP_SMC_STATUS_OK 473 */ 474 #define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS 21 475 #define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS \ 476 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS) 477 478 /* 479 * Request INTEL_SIP_SMC_HPS_SET_BRIDGES 480 * 481 * Enable/disable the SoC FPGA bridges 482 * 483 * Call register usage: 484 * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES 485 * a1 Set bridges status: 486 * Bit 0: 0 - Disable, 1 - Enable 487 * Bit 1: 1 - Has mask value in a2 488 * a2 Mask value 489 * Bit 0: soc2fpga 490 * Bit 1: lwhps2fpga 491 * Bit 2: fpga2soc 492 * Bit 3: f2sdram0 (For Stratix 10 only) 493 * Bit 4: f2sdram1 (For Stratix 10 only) 494 * Bit 5: f2sdram2 (For Stratix 10 only) 495 * a3-7 not used 496 * Return status 497 * a0 INTEL_SIP_SMC_STATUS_OK 498 */ 499 #define INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES 50 500 #define INTEL_SIP_SMC_HPS_SET_BRIDGES \ 501 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES) 502 503 /* 504 * Request INTEL_SIP_SMC_MBOX_SEND_CMD 505 * 506 * Send mailbox command to SDM 507 * 508 * Call register usage: 509 * a0 INTEL_SIP_SMC_MBOX_SEND_CMD 510 * a1 Mailbox command 511 * a2 64bit physical address pointer to command's arguments 512 * a3 Length of the argument 513 * a4 Urgent command: 514 * 0 - Disable 515 * 1 - Enable 516 * a5 64bit physical address pointer to a buffer for receiving responses 517 * a6 Length of the buffer 518 * 519 * Return status 520 * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR 521 * a1 Status of mailbox response 522 * a2 Received length in the buffer 523 */ 524 #define INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD 60 525 #define INTEL_SIP_SMC_MBOX_SEND_CMD \ 526 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD) 527 528 /* 529 * Request INTEL_SIP_SMC_GET_USERCODE 530 * 531 * Send mailbox command to get usercode from SDM 532 * 533 * Call register usage: 534 * a0 INTEL_SIP_SMC_GET_USERCODE 535 * a1-7 not used. 536 * 537 * Return status 538 * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR 539 * a1 User code 540 * a2-3 not used. 541 */ 542 #define INTEL_SIP_SMC_FUNCID_GET_USERCODE 61 543 #define INTEL_SIP_SMC_GET_USERCODE \ 544 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_GET_USERCODE) 545 546 #endif 547