1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
4 * Steven J. Hill <sjhill@realitydiluted.com>
5 * Thomas Gleixner <tglx@linutronix.de>
6 *
7 * Info:
8 * Contains standard defines and IDs for NAND flash devices
9 *
10 * Changelog:
11 * See git changelog.
12 */
13 #ifndef __LINUX_MTD_RAWNAND_H
14 #define __LINUX_MTD_RAWNAND_H
15
16 #include <config.h>
17
18 #include <dm/device.h>
19 #include <linux/bitops.h>
20 #include <linux/compat.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/flashchip.h>
23 #include <linux/mtd/bbm.h>
24 #include <asm/cache.h>
25
26 struct mtd_info;
27 struct nand_chip;
28 struct nand_flash_dev;
29 struct device_node;
30
31 /* Get the flash and manufacturer id and lookup if the type is supported. */
32 int nand_detect(struct nand_chip *chip, int *maf_id, int *dev_id,
33 struct nand_flash_dev *type);
34
35 /* Scan and identify a NAND device */
36 int nand_scan(struct mtd_info *mtd, int max_chips);
37 /*
38 * Separate phases of nand_scan(), allowing board driver to intervene
39 * and override command or ECC setup according to flash type.
40 */
41 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
42 struct nand_flash_dev *table);
43 int nand_scan_tail(struct mtd_info *mtd);
44
45 /* Free resources held by the NAND device */
46 void nand_release(struct mtd_info *mtd);
47
48 /* Internal helper for board drivers which need to override command function */
49 void nand_wait_ready(struct mtd_info *mtd);
50
51 /*
52 * This constant declares the max. oobsize / page, which
53 * is supported now. If you add a chip with bigger oobsize/page
54 * adjust this accordingly.
55 */
56 #define NAND_MAX_OOBSIZE 1664
57 #define NAND_MAX_PAGESIZE 16384
58
59 /*
60 * Constants for hardware specific CLE/ALE/NCE function
61 *
62 * These are bits which can be or'ed to set/clear multiple
63 * bits in one go.
64 */
65 /* Select the chip by setting nCE to low */
66 #define NAND_NCE 0x01
67 /* Select the command latch by setting CLE to high */
68 #define NAND_CLE 0x02
69 /* Select the address latch by setting ALE to high */
70 #define NAND_ALE 0x04
71
72 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
73 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
74 #define NAND_CTRL_CHANGE 0x80
75
76 /*
77 * Standard NAND flash commands
78 */
79 #define NAND_CMD_READ0 0
80 #define NAND_CMD_READ1 1
81 #define NAND_CMD_RNDOUT 5
82 #define NAND_CMD_PAGEPROG 0x10
83 #define NAND_CMD_READOOB 0x50
84 #define NAND_CMD_ERASE1 0x60
85 #define NAND_CMD_STATUS 0x70
86 #define NAND_CMD_SEQIN 0x80
87 #define NAND_CMD_RNDIN 0x85
88 #define NAND_CMD_READID 0x90
89 #define NAND_CMD_ERASE2 0xd0
90 #define NAND_CMD_PARAM 0xec
91 #define NAND_CMD_GET_FEATURES 0xee
92 #define NAND_CMD_SET_FEATURES 0xef
93 #define NAND_CMD_RESET 0xff
94
95 #define NAND_CMD_LOCK 0x2a
96 #define NAND_CMD_UNLOCK1 0x23
97 #define NAND_CMD_UNLOCK2 0x24
98
99 /* Extended commands for large page devices */
100 #define NAND_CMD_READSTART 0x30
101 #define NAND_CMD_RNDOUTSTART 0xE0
102 #define NAND_CMD_CACHEDPROG 0x15
103
104 /* Extended commands for AG-AND device */
105 /*
106 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
107 * there is no way to distinguish that from NAND_CMD_READ0
108 * until the remaining sequence of commands has been completed
109 * so add a high order bit and mask it off in the command.
110 */
111 #define NAND_CMD_DEPLETE1 0x100
112 #define NAND_CMD_DEPLETE2 0x38
113 #define NAND_CMD_STATUS_MULTI 0x71
114 #define NAND_CMD_STATUS_ERROR 0x72
115 /* multi-bank error status (banks 0-3) */
116 #define NAND_CMD_STATUS_ERROR0 0x73
117 #define NAND_CMD_STATUS_ERROR1 0x74
118 #define NAND_CMD_STATUS_ERROR2 0x75
119 #define NAND_CMD_STATUS_ERROR3 0x76
120 #define NAND_CMD_STATUS_RESET 0x7f
121 #define NAND_CMD_STATUS_CLEAR 0xff
122
123 #define NAND_CMD_NONE -1
124
125 /* Status bits */
126 #define NAND_STATUS_FAIL 0x01
127 #define NAND_STATUS_FAIL_N1 0x02
128 #define NAND_STATUS_TRUE_READY 0x20
129 #define NAND_STATUS_READY 0x40
130 #define NAND_STATUS_WP 0x80
131
132 #define NAND_DATA_IFACE_CHECK_ONLY -1
133
134 /*
135 * There are different places where the manufacturer stores the factory bad
136 * block markers.
137 *
138 * Position within the block: Each of these pages needs to be checked for a
139 * bad block marking pattern.
140 */
141 #define NAND_BBM_FIRSTPAGE BIT(24)
142 #define NAND_BBM_SECONDPAGE BIT(25)
143 #define NAND_BBM_LASTPAGE BIT(26)
144
145 /*
146 * Constants for ECC_MODES
147 */
148 typedef enum {
149 NAND_ECC_NONE,
150 NAND_ECC_SOFT,
151 NAND_ECC_HW,
152 NAND_ECC_HW_SYNDROME,
153 NAND_ECC_HW_OOB_FIRST,
154 NAND_ECC_SOFT_BCH,
155 } nand_ecc_modes_t;
156
157 enum nand_ecc_algo {
158 NAND_ECC_UNKNOWN,
159 NAND_ECC_HAMMING,
160 NAND_ECC_BCH,
161 };
162
163 /*
164 * Constants for Hardware ECC
165 */
166 /* Reset Hardware ECC for read */
167 #define NAND_ECC_READ 0
168 /* Reset Hardware ECC for write */
169 #define NAND_ECC_WRITE 1
170 /* Enable Hardware ECC before syndrome is read back from flash */
171 #define NAND_ECC_READSYN 2
172
173 /*
174 * Enable generic NAND 'page erased' check. This check is only done when
175 * ecc.correct() returns -EBADMSG.
176 * Set this flag if your implementation does not fix bitflips in erased
177 * pages and you want to rely on the default implementation.
178 */
179 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
180 #define NAND_ECC_MAXIMIZE BIT(1)
181 /*
182 * If your controller already sends the required NAND commands when
183 * reading or writing a page, then the framework is not supposed to
184 * send READ0 and SEQIN/PAGEPROG respectively.
185 */
186 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
187
188 /* Bit mask for flags passed to do_nand_read_ecc */
189 #define NAND_GET_DEVICE 0x80
190
191 /*
192 * Option constants for bizarre disfunctionality and real
193 * features.
194 */
195 /* Buswidth is 16 bit */
196 #define NAND_BUSWIDTH_16 0x00000002
197 /* Device supports partial programming without padding */
198 #define NAND_NO_PADDING 0x00000004
199 /* Chip has cache program function */
200 #define NAND_CACHEPRG 0x00000008
201 /* Chip has copy back function */
202 #define NAND_COPYBACK 0x00000010
203 /*
204 * Chip requires ready check on read (for auto-incremented sequential read).
205 * True only for small page devices; large page devices do not support
206 * autoincrement.
207 */
208 #define NAND_NEED_READRDY 0x00000100
209
210 /* Chip does not allow subpage writes */
211 #define NAND_NO_SUBPAGE_WRITE 0x00000200
212
213 /* Device is one of 'new' xD cards that expose fake nand command set */
214 #define NAND_BROKEN_XD 0x00000400
215
216 /* Device behaves just like nand, but is readonly */
217 #define NAND_ROM 0x00000800
218
219 /* Device supports subpage reads */
220 #define NAND_SUBPAGE_READ 0x00001000
221
222 /*
223 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
224 * patterns.
225 */
226 #define NAND_NEED_SCRAMBLING 0x00002000
227
228 /* Device needs 3rd row address cycle */
229 #define NAND_ROW_ADDR_3 0x00004000
230
231 /* Options valid for Samsung large page devices */
232 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
233
234 /* Macros to identify the above */
235 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
236 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
237 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
238
239 /* Non chip related options */
240 /* This option skips the bbt scan during initialization. */
241 #define NAND_SKIP_BBTSCAN 0x00010000
242 /*
243 * This option is defined if the board driver allocates its own buffers
244 * (e.g. because it needs them DMA-coherent).
245 */
246 #define NAND_OWN_BUFFERS 0x00020000
247 /* Chip may not exist, so silence any errors in scan */
248 #define NAND_SCAN_SILENT_NODEV 0x00040000
249 /*
250 * Autodetect nand buswidth with readid/onfi.
251 * This suppose the driver will configure the hardware in 8 bits mode
252 * when calling nand_scan_ident, and update its configuration
253 * before calling nand_scan_tail.
254 */
255 #define NAND_BUSWIDTH_AUTO 0x00080000
256 /*
257 * This option could be defined by controller drivers to protect against
258 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
259 */
260 #define NAND_USE_BOUNCE_BUFFER 0x00100000
261 /*
262 * Whether the NAND chip is a boot medium. Drivers might use this information
263 * to select ECC algorithms supported by the boot ROM or similar restrictions.
264 */
265 #define NAND_IS_BOOT_MEDIUM 0x00400000
266
267 /*
268 * Do not try to tweak the timings at runtime. This is needed when the
269 * controller initializes the timings on itself or when it relies on
270 * configuration done by the bootloader.
271 */
272 #define NAND_KEEP_TIMINGS 0x00800000
273
274 /* Options set by nand scan */
275 /* bbt has already been read */
276 #define NAND_BBT_SCANNED 0x40000000
277 /* Nand scan has allocated controller struct */
278 #define NAND_CONTROLLER_ALLOC 0x80000000
279
280 /* Cell info constants */
281 #define NAND_CI_CHIPNR_MSK 0x03
282 #define NAND_CI_CELLTYPE_MSK 0x0C
283 #define NAND_CI_CELLTYPE_SHIFT 2
284
285 /* ONFI features */
286 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
287 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
288
289 /* ONFI timing mode, used in both asynchronous and synchronous mode */
290 #define ONFI_TIMING_MODE_0 (1 << 0)
291 #define ONFI_TIMING_MODE_1 (1 << 1)
292 #define ONFI_TIMING_MODE_2 (1 << 2)
293 #define ONFI_TIMING_MODE_3 (1 << 3)
294 #define ONFI_TIMING_MODE_4 (1 << 4)
295 #define ONFI_TIMING_MODE_5 (1 << 5)
296 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
297
298 /* ONFI feature address */
299 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
300
301 /* Vendor-specific feature address (Micron) */
302 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
303
304 /* ONFI subfeature parameters length */
305 #define ONFI_SUBFEATURE_PARAM_LEN 4
306
307 /* ONFI optional commands SET/GET FEATURES supported? */
308 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
309
310 struct nand_onfi_params {
311 /* rev info and features block */
312 /* 'O' 'N' 'F' 'I' */
313 u8 sig[4];
314 __le16 revision;
315 __le16 features;
316 __le16 opt_cmd;
317 u8 reserved0[2];
318 __le16 ext_param_page_length; /* since ONFI 2.1 */
319 u8 num_of_param_pages; /* since ONFI 2.1 */
320 u8 reserved1[17];
321
322 /* manufacturer information block */
323 char manufacturer[12];
324 char model[20];
325 u8 jedec_id;
326 __le16 date_code;
327 u8 reserved2[13];
328
329 /* memory organization block */
330 __le32 byte_per_page;
331 __le16 spare_bytes_per_page;
332 __le32 data_bytes_per_ppage;
333 __le16 spare_bytes_per_ppage;
334 __le32 pages_per_block;
335 __le32 blocks_per_lun;
336 u8 lun_count;
337 u8 addr_cycles;
338 u8 bits_per_cell;
339 __le16 bb_per_lun;
340 __le16 block_endurance;
341 u8 guaranteed_good_blocks;
342 __le16 guaranteed_block_endurance;
343 u8 programs_per_page;
344 u8 ppage_attr;
345 u8 ecc_bits;
346 u8 interleaved_bits;
347 u8 interleaved_ops;
348 u8 reserved3[13];
349
350 /* electrical parameter block */
351 u8 io_pin_capacitance_max;
352 __le16 async_timing_mode;
353 __le16 program_cache_timing_mode;
354 __le16 t_prog;
355 __le16 t_bers;
356 __le16 t_r;
357 __le16 t_ccs;
358 __le16 src_sync_timing_mode;
359 u8 src_ssync_features;
360 __le16 clk_pin_capacitance_typ;
361 __le16 io_pin_capacitance_typ;
362 __le16 input_pin_capacitance_typ;
363 u8 input_pin_capacitance_max;
364 u8 driver_strength_support;
365 __le16 t_int_r;
366 __le16 t_adl;
367 u8 reserved4[8];
368
369 /* vendor */
370 __le16 vendor_revision;
371 u8 vendor[88];
372
373 __le16 crc;
374 } __packed;
375
376 #define ONFI_CRC_BASE 0x4F4E
377
378 /* Extended ECC information Block Definition (since ONFI 2.1) */
379 struct onfi_ext_ecc_info {
380 u8 ecc_bits;
381 u8 codeword_size;
382 __le16 bb_per_lun;
383 __le16 block_endurance;
384 u8 reserved[2];
385 } __packed;
386
387 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
388 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
389 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
390 struct onfi_ext_section {
391 u8 type;
392 u8 length;
393 } __packed;
394
395 #define ONFI_EXT_SECTION_MAX 8
396
397 /* Extended Parameter Page Definition (since ONFI 2.1) */
398 struct onfi_ext_param_page {
399 __le16 crc;
400 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
401 u8 reserved0[10];
402 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
403
404 /*
405 * The actual size of the Extended Parameter Page is in
406 * @ext_param_page_length of nand_onfi_params{}.
407 * The following are the variable length sections.
408 * So we do not add any fields below. Please see the ONFI spec.
409 */
410 } __packed;
411
412 struct jedec_ecc_info {
413 u8 ecc_bits;
414 u8 codeword_size;
415 __le16 bb_per_lun;
416 __le16 block_endurance;
417 u8 reserved[2];
418 } __packed;
419
420 /* JEDEC features */
421 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
422
423 struct nand_jedec_params {
424 /* rev info and features block */
425 /* 'J' 'E' 'S' 'D' */
426 u8 sig[4];
427 __le16 revision;
428 __le16 features;
429 u8 opt_cmd[3];
430 __le16 sec_cmd;
431 u8 num_of_param_pages;
432 u8 reserved0[18];
433
434 /* manufacturer information block */
435 char manufacturer[12];
436 char model[20];
437 u8 jedec_id[6];
438 u8 reserved1[10];
439
440 /* memory organization block */
441 __le32 byte_per_page;
442 __le16 spare_bytes_per_page;
443 u8 reserved2[6];
444 __le32 pages_per_block;
445 __le32 blocks_per_lun;
446 u8 lun_count;
447 u8 addr_cycles;
448 u8 bits_per_cell;
449 u8 programs_per_page;
450 u8 multi_plane_addr;
451 u8 multi_plane_op_attr;
452 u8 reserved3[38];
453
454 /* electrical parameter block */
455 __le16 async_sdr_speed_grade;
456 __le16 toggle_ddr_speed_grade;
457 __le16 sync_ddr_speed_grade;
458 u8 async_sdr_features;
459 u8 toggle_ddr_features;
460 u8 sync_ddr_features;
461 __le16 t_prog;
462 __le16 t_bers;
463 __le16 t_r;
464 __le16 t_r_multi_plane;
465 __le16 t_ccs;
466 __le16 io_pin_capacitance_typ;
467 __le16 input_pin_capacitance_typ;
468 __le16 clk_pin_capacitance_typ;
469 u8 driver_strength_support;
470 __le16 t_adl;
471 u8 reserved4[36];
472
473 /* ECC and endurance block */
474 u8 guaranteed_good_blocks;
475 __le16 guaranteed_block_endurance;
476 struct jedec_ecc_info ecc_info[4];
477 u8 reserved5[29];
478
479 /* reserved */
480 u8 reserved6[148];
481
482 /* vendor */
483 __le16 vendor_rev_num;
484 u8 reserved7[88];
485
486 /* CRC for Parameter Page */
487 __le16 crc;
488 } __packed;
489
490 /**
491 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
492 * @lock: protection lock
493 * @active: the mtd device which holds the controller currently
494 * @wq: wait queue to sleep on if a NAND operation is in
495 * progress used instead of the per chip wait queue
496 * when a hw controller is available.
497 */
498 struct nand_hw_control {
499 spinlock_t lock;
500 struct nand_chip *active;
501 };
502
nand_hw_control_init(struct nand_hw_control * nfc)503 static inline void nand_hw_control_init(struct nand_hw_control *nfc)
504 {
505 nfc->active = NULL;
506 spin_lock_init(&nfc->lock);
507 init_waitqueue_head(&nfc->wq);
508 }
509
510 /* The maximum expected count of bytes in the NAND ID sequence */
511 #define NAND_MAX_ID_LEN 8
512
513 /**
514 * struct nand_id - NAND id structure
515 * @data: buffer containing the id bytes.
516 * @len: ID length.
517 */
518 struct nand_id {
519 u8 data[NAND_MAX_ID_LEN];
520 int len;
521 };
522
523 /**
524 * struct nand_ecc_step_info - ECC step information of ECC engine
525 * @stepsize: data bytes per ECC step
526 * @strengths: array of supported strengths
527 * @nstrengths: number of supported strengths
528 */
529 struct nand_ecc_step_info {
530 int stepsize;
531 const int *strengths;
532 int nstrengths;
533 };
534
535 /**
536 * struct nand_ecc_caps - capability of ECC engine
537 * @stepinfos: array of ECC step information
538 * @nstepinfos: number of ECC step information
539 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
540 */
541 struct nand_ecc_caps {
542 const struct nand_ecc_step_info *stepinfos;
543 int nstepinfos;
544 int (*calc_ecc_bytes)(int step_size, int strength);
545 };
546
547 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
548 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
549 static const int __name##_strengths[] = { __VA_ARGS__ }; \
550 static const struct nand_ecc_step_info __name##_stepinfo = { \
551 .stepsize = __step, \
552 .strengths = __name##_strengths, \
553 .nstrengths = ARRAY_SIZE(__name##_strengths), \
554 }; \
555 static const struct nand_ecc_caps __name = { \
556 .stepinfos = &__name##_stepinfo, \
557 .nstepinfos = 1, \
558 .calc_ecc_bytes = __calc, \
559 }
560
561 /**
562 * struct nand_ecc_ctrl - Control structure for ECC
563 * @mode: ECC mode
564 * @algo: ECC algorithm
565 * @steps: number of ECC steps per page
566 * @size: data bytes per ECC step
567 * @bytes: ECC bytes per step
568 * @strength: max number of correctible bits per ECC step
569 * @total: total number of ECC bytes per page
570 * @prepad: padding information for syndrome based ECC generators
571 * @postpad: padding information for syndrome based ECC generators
572 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
573 * @layout: ECC layout control struct pointer
574 * @priv: pointer to private ECC control data
575 * @hwctl: function to control hardware ECC generator. Must only
576 * be provided if an hardware ECC is available
577 * @calculate: function for ECC calculation or readback from ECC hardware
578 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
579 * Should return a positive number representing the number of
580 * corrected bitflips, -EBADMSG if the number of bitflips exceed
581 * ECC strength, or any other error code if the error is not
582 * directly related to correction.
583 * If -EBADMSG is returned the input buffers should be left
584 * untouched.
585 * @read_page_raw: function to read a raw page without ECC. This function
586 * should hide the specific layout used by the ECC
587 * controller and always return contiguous in-band and
588 * out-of-band data even if they're not stored
589 * contiguously on the NAND chip (e.g.
590 * NAND_ECC_HW_SYNDROME interleaves in-band and
591 * out-of-band data).
592 * @write_page_raw: function to write a raw page without ECC. This function
593 * should hide the specific layout used by the ECC
594 * controller and consider the passed data as contiguous
595 * in-band and out-of-band data. ECC controller is
596 * responsible for doing the appropriate transformations
597 * to adapt to its specific layout (e.g.
598 * NAND_ECC_HW_SYNDROME interleaves in-band and
599 * out-of-band data).
600 * @read_page: function to read a page according to the ECC generator
601 * requirements; returns maximum number of bitflips corrected in
602 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
603 * @read_subpage: function to read parts of the page covered by ECC;
604 * returns same as read_page()
605 * @write_subpage: function to write parts of the page covered by ECC.
606 * @write_page: function to write a page according to the ECC generator
607 * requirements.
608 * @write_oob_raw: function to write chip OOB data without ECC
609 * @read_oob_raw: function to read chip OOB data without ECC
610 * @read_oob: function to read chip OOB data
611 * @write_oob: function to write chip OOB data
612 */
613 struct nand_ecc_ctrl {
614 nand_ecc_modes_t mode;
615 enum nand_ecc_algo algo;
616 int steps;
617 int size;
618 int bytes;
619 int total;
620 int strength;
621 int prepad;
622 int postpad;
623 unsigned int options;
624 struct nand_ecclayout *layout;
625 void *priv;
626 void (*hwctl)(struct mtd_info *mtd, int mode);
627 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
628 uint8_t *ecc_code);
629 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
630 uint8_t *calc_ecc);
631 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
632 uint8_t *buf, int oob_required, int page);
633 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
634 const uint8_t *buf, int oob_required, int page);
635 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
636 uint8_t *buf, int oob_required, int page);
637 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
638 uint32_t offs, uint32_t len, uint8_t *buf, int page);
639 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
640 uint32_t offset, uint32_t data_len,
641 const uint8_t *data_buf, int oob_required, int page);
642 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
643 const uint8_t *buf, int oob_required, int page);
644 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
645 int page);
646 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
647 int page);
648 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
649 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
650 int page);
651 };
652
nand_standard_page_accessors(struct nand_ecc_ctrl * ecc)653 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
654 {
655 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
656 }
657
658 /**
659 * struct nand_buffers - buffer structure for read/write
660 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
661 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
662 * @databuf: buffer pointer for data, size is (page size + oobsize).
663 *
664 * Do not change the order of buffers. databuf and oobrbuf must be in
665 * consecutive order.
666 */
667 struct nand_buffers {
668 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
669 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
670 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
671 ARCH_DMA_MINALIGN)];
672 };
673
674 /**
675 * struct nand_sdr_timings - SDR NAND chip timings
676 *
677 * This struct defines the timing requirements of a SDR NAND chip.
678 * These information can be found in every NAND datasheets and the timings
679 * meaning are described in the ONFI specifications:
680 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
681 * Parameters)
682 *
683 * All these timings are expressed in picoseconds.
684 *
685 * @tBERS_max: Block erase time
686 * @tCCS_min: Change column setup time
687 * @tPROG_max: Page program time
688 * @tR_max: Page read time
689 * @tALH_min: ALE hold time
690 * @tADL_min: ALE to data loading time
691 * @tALS_min: ALE setup time
692 * @tAR_min: ALE to RE# delay
693 * @tCEA_max: CE# access time
694 * @tCEH_min: CE# high hold time
695 * @tCH_min: CE# hold time
696 * @tCHZ_max: CE# high to output hi-Z
697 * @tCLH_min: CLE hold time
698 * @tCLR_min: CLE to RE# delay
699 * @tCLS_min: CLE setup time
700 * @tCOH_min: CE# high to output hold
701 * @tCS_min: CE# setup time
702 * @tDH_min: Data hold time
703 * @tDS_min: Data setup time
704 * @tFEAT_max: Busy time for Set Features and Get Features
705 * @tIR_min: Output hi-Z to RE# low
706 * @tITC_max: Interface and Timing Mode Change time
707 * @tRC_min: RE# cycle time
708 * @tREA_max: RE# access time
709 * @tREH_min: RE# high hold time
710 * @tRHOH_min: RE# high to output hold
711 * @tRHW_min: RE# high to WE# low
712 * @tRHZ_max: RE# high to output hi-Z
713 * @tRLOH_min: RE# low to output hold
714 * @tRP_min: RE# pulse width
715 * @tRR_min: Ready to RE# low (data only)
716 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
717 * rising edge of R/B#.
718 * @tWB_max: WE# high to SR[6] low
719 * @tWC_min: WE# cycle time
720 * @tWH_min: WE# high hold time
721 * @tWHR_min: WE# high to RE# low
722 * @tWP_min: WE# pulse width
723 * @tWW_min: WP# transition to WE# low
724 */
725 struct nand_sdr_timings {
726 u64 tBERS_max;
727 u32 tCCS_min;
728 u64 tPROG_max;
729 u64 tR_max;
730 u32 tALH_min;
731 u32 tADL_min;
732 u32 tALS_min;
733 u32 tAR_min;
734 u32 tCEA_max;
735 u32 tCEH_min;
736 u32 tCH_min;
737 u32 tCHZ_max;
738 u32 tCLH_min;
739 u32 tCLR_min;
740 u32 tCLS_min;
741 u32 tCOH_min;
742 u32 tCS_min;
743 u32 tDH_min;
744 u32 tDS_min;
745 u32 tFEAT_max;
746 u32 tIR_min;
747 u32 tITC_max;
748 u32 tRC_min;
749 u32 tREA_max;
750 u32 tREH_min;
751 u32 tRHOH_min;
752 u32 tRHW_min;
753 u32 tRHZ_max;
754 u32 tRLOH_min;
755 u32 tRP_min;
756 u32 tRR_min;
757 u64 tRST_max;
758 u32 tWB_max;
759 u32 tWC_min;
760 u32 tWH_min;
761 u32 tWHR_min;
762 u32 tWP_min;
763 u32 tWW_min;
764 };
765
766 /**
767 * enum nand_data_interface_type - NAND interface timing type
768 * @NAND_SDR_IFACE: Single Data Rate interface
769 */
770 enum nand_data_interface_type {
771 NAND_SDR_IFACE,
772 };
773
774 /**
775 * struct nand_data_interface - NAND interface timing
776 * @type: type of the timing
777 * @timings: The timing, type according to @type
778 */
779 struct nand_data_interface {
780 enum nand_data_interface_type type;
781 union {
782 struct nand_sdr_timings sdr;
783 } timings;
784 };
785
786 /**
787 * nand_get_sdr_timings - get SDR timing from data interface
788 * @conf: The data interface
789 */
790 static inline const struct nand_sdr_timings *
nand_get_sdr_timings(const struct nand_data_interface * conf)791 nand_get_sdr_timings(const struct nand_data_interface *conf)
792 {
793 if (conf->type != NAND_SDR_IFACE)
794 return ERR_PTR(-EINVAL);
795
796 return &conf->timings.sdr;
797 }
798
799 /**
800 * struct nand_manufacturer_ops - NAND Manufacturer operations
801 * @detect: detect the NAND memory organization and capabilities
802 * @init: initialize all vendor specific fields (like the ->read_retry()
803 * implementation) if any.
804 */
805 struct nand_manufacturer_ops {
806 void (*detect)(struct nand_chip *chip);
807 int (*init)(struct nand_chip *chip);
808 };
809
810 /**
811 * struct nand_chip - NAND Private Flash Chip Data
812 * @mtd: MTD device registered to the MTD framework
813 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
814 * flash device
815 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
816 * flash device.
817 * @flash_node: [BOARDSPECIFIC] device node describing this instance
818 * @read_byte: [REPLACEABLE] read one byte from the chip
819 * @read_word: [REPLACEABLE] read one word from the chip
820 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
821 * low 8 I/O lines
822 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
823 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
824 * @select_chip: [REPLACEABLE] select chip nr
825 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
826 * @block_markbad: [REPLACEABLE] mark a block bad
827 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
828 * ALE/CLE/nCE. Also used to write command and address
829 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
830 * device ready/busy line. If set to NULL no access to
831 * ready/busy is available and the ready/busy information
832 * is read from the chip status register.
833 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
834 * commands to the chip.
835 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
836 * ready.
837 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
838 * setting the read-retry mode. Mostly needed for MLC NAND.
839 * @ecc: [BOARDSPECIFIC] ECC control structure
840 * @buffers: buffer structure for read/write
841 * @buf_align: minimum buffer alignment required by a platform
842 * @hwcontrol: platform-specific hardware control structure
843 * @erase: [REPLACEABLE] erase function
844 * @scan_bbt: [REPLACEABLE] function to scan bad block table
845 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
846 * data from array to read regs (tR).
847 * @state: [INTERN] the current state of the NAND device
848 * @oob_poi: "poison value buffer," used for laying out OOB data
849 * before writing
850 * @page_shift: [INTERN] number of address bits in a page (column
851 * address bits).
852 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
853 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
854 * @chip_shift: [INTERN] number of address bits in one chip
855 * @options: [BOARDSPECIFIC] various chip options. They can partly
856 * be set to inform nand_scan about special functionality.
857 * See the defines for further explanation.
858 * @bbt_options: [INTERN] bad block specific options. All options used
859 * here must come from bbm.h. By default, these options
860 * will be copied to the appropriate nand_bbt_descr's.
861 * @badblockpos: [INTERN] position of the bad block marker in the oob
862 * area.
863 * @badblockbits: [INTERN] minimum number of set bits in a good block's
864 * bad block marker position; i.e., BBM == 11110111b is
865 * not bad when badblockbits == 7
866 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
867 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
868 * Minimum amount of bit errors per @ecc_step_ds guaranteed
869 * to be correctable. If unknown, set to zero.
870 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
871 * also from the datasheet. It is the recommended ECC step
872 * size, if known; if unknown, set to zero.
873 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
874 * set to the actually used ONFI mode if the chip is
875 * ONFI compliant or deduced from the datasheet if
876 * the NAND chip is not ONFI compliant.
877 * @numchips: [INTERN] number of physical chips
878 * @chipsize: [INTERN] the size of one chip for multichip arrays
879 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
880 * @pagebuf: [INTERN] holds the pagenumber which is currently in
881 * data_buf.
882 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
883 * currently in data_buf.
884 * @subpagesize: [INTERN] holds the subpagesize
885 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
886 * non 0 if ONFI supported.
887 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
888 * non 0 if JEDEC supported.
889 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
890 * supported, 0 otherwise.
891 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
892 * supported, 0 otherwise.
893 * @read_retries: [INTERN] the number of read retry modes supported
894 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
895 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
896 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
897 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
898 * means the configuration should not be applied but
899 * only checked.
900 * @bbt: [INTERN] bad block table pointer
901 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
902 * lookup.
903 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
904 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
905 * bad block scan.
906 * @controller: [REPLACEABLE] a pointer to a hardware controller
907 * structure which is shared among multiple independent
908 * devices.
909 * @priv: [OPTIONAL] pointer to private chip data
910 * @write_page: [REPLACEABLE] High-level page write function
911 * @manufacturer: [INTERN] Contains manufacturer information
912 */
913
914 struct nand_chip {
915 struct mtd_info mtd;
916 struct nand_id id;
917
918 void __iomem *IO_ADDR_R;
919 void __iomem *IO_ADDR_W;
920
921 ofnode flash_node;
922
923 uint8_t (*read_byte)(struct mtd_info *mtd);
924 u16 (*read_word)(struct mtd_info *mtd);
925 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
926 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
927 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
928 void (*select_chip)(struct mtd_info *mtd, int chip);
929 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
930 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
931 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
932 int (*dev_ready)(struct mtd_info *mtd);
933 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
934 int page_addr);
935 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
936 int (*erase)(struct mtd_info *mtd, int page);
937 int (*scan_bbt)(struct mtd_info *mtd);
938 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
939 uint32_t offset, int data_len, const uint8_t *buf,
940 int oob_required, int page, int raw);
941 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
942 int feature_addr, uint8_t *subfeature_para);
943 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
944 int feature_addr, uint8_t *subfeature_para);
945 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
946 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
947 const struct nand_data_interface *conf);
948
949 int chip_delay;
950 unsigned int options;
951 unsigned int bbt_options;
952
953 int page_shift;
954 int phys_erase_shift;
955 int bbt_erase_shift;
956 int chip_shift;
957 int numchips;
958 uint64_t chipsize;
959 int pagemask;
960 int pagebuf;
961 unsigned int pagebuf_bitflips;
962 int subpagesize;
963 uint8_t bits_per_cell;
964 uint16_t ecc_strength_ds;
965 uint16_t ecc_step_ds;
966 int onfi_timing_mode_default;
967 int badblockpos;
968 int badblockbits;
969
970 int onfi_version;
971 int jedec_version;
972 struct nand_onfi_params onfi_params;
973 struct nand_jedec_params jedec_params;
974
975 struct nand_data_interface *data_interface;
976
977 int read_retries;
978
979 flstate_t state;
980
981 uint8_t *oob_poi;
982 struct nand_hw_control *controller;
983 struct nand_ecclayout *ecclayout;
984
985 struct nand_ecc_ctrl ecc;
986 struct nand_buffers *buffers;
987 unsigned long buf_align;
988 struct nand_hw_control hwcontrol;
989
990 uint8_t *bbt;
991 struct nand_bbt_descr *bbt_td;
992 struct nand_bbt_descr *bbt_md;
993
994 struct nand_bbt_descr *badblock_pattern;
995 int cur_cs;
996
997 void *priv;
998
999 struct {
1000 const struct nand_manufacturer *desc;
1001 void *priv;
1002 } manufacturer;
1003 };
1004
nand_set_flash_node(struct nand_chip * chip,ofnode node)1005 static inline void nand_set_flash_node(struct nand_chip *chip,
1006 ofnode node)
1007 {
1008 chip->flash_node = node;
1009 }
1010
nand_get_flash_node(struct nand_chip * chip)1011 static inline ofnode nand_get_flash_node(struct nand_chip *chip)
1012 {
1013 return chip->flash_node;
1014 }
1015
mtd_to_nand(struct mtd_info * mtd)1016 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1017 {
1018 return container_of(mtd, struct nand_chip, mtd);
1019 }
1020
nand_to_mtd(struct nand_chip * chip)1021 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1022 {
1023 return &chip->mtd;
1024 }
1025
nand_get_controller_data(struct nand_chip * chip)1026 static inline void *nand_get_controller_data(struct nand_chip *chip)
1027 {
1028 return chip->priv;
1029 }
1030
nand_set_controller_data(struct nand_chip * chip,void * priv)1031 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1032 {
1033 chip->priv = priv;
1034 }
1035
nand_set_manufacturer_data(struct nand_chip * chip,void * priv)1036 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1037 void *priv)
1038 {
1039 chip->manufacturer.priv = priv;
1040 }
1041
nand_get_manufacturer_data(struct nand_chip * chip)1042 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1043 {
1044 return chip->manufacturer.priv;
1045 }
1046
1047 /*
1048 * NAND Flash Manufacturer ID Codes
1049 */
1050 #define NAND_MFR_TOSHIBA 0x98
1051 #define NAND_MFR_SAMSUNG 0xec
1052 #define NAND_MFR_FUJITSU 0x04
1053 #define NAND_MFR_NATIONAL 0x8f
1054 #define NAND_MFR_RENESAS 0x07
1055 #define NAND_MFR_STMICRO 0x20
1056 #define NAND_MFR_HYNIX 0xad
1057 #define NAND_MFR_MICRON 0x2c
1058 #define NAND_MFR_AMD 0x01
1059 #define NAND_MFR_MACRONIX 0xc2
1060 #define NAND_MFR_EON 0x92
1061 #define NAND_MFR_SANDISK 0x45
1062 #define NAND_MFR_INTEL 0x89
1063 #define NAND_MFR_ATO 0x9b
1064
1065 /* The maximum expected count of bytes in the NAND ID sequence */
1066 #define NAND_MAX_ID_LEN 8
1067
1068 /*
1069 * A helper for defining older NAND chips where the second ID byte fully
1070 * defined the chip, including the geometry (chip size, eraseblock size, page
1071 * size). All these chips have 512 bytes NAND page size.
1072 */
1073 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1074 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1075 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1076
1077 /*
1078 * A helper for defining newer chips which report their page size and
1079 * eraseblock size via the extended ID bytes.
1080 *
1081 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1082 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1083 * device ID now only represented a particular total chip size (and voltage,
1084 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1085 * using the same device ID.
1086 */
1087 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1088 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1089 .options = (opts) }
1090
1091 #define NAND_ECC_INFO(_strength, _step) \
1092 { .strength_ds = (_strength), .step_ds = (_step) }
1093 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1094 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1095
1096 /**
1097 * struct nand_flash_dev - NAND Flash Device ID Structure
1098 * @name: a human-readable name of the NAND chip
1099 * @dev_id: the device ID (the second byte of the full chip ID array)
1100 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1101 * memory address as @id[0])
1102 * @dev_id: device ID part of the full chip ID array (refers the same memory
1103 * address as @id[1])
1104 * @id: full device ID array
1105 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1106 * well as the eraseblock size) is determined from the extended NAND
1107 * chip ID array)
1108 * @chipsize: total chip size in MiB
1109 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1110 * @options: stores various chip bit options
1111 * @id_len: The valid length of the @id.
1112 * @oobsize: OOB size
1113 * @ecc: ECC correctability and step information from the datasheet.
1114 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1115 * @ecc_strength_ds in nand_chip{}.
1116 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1117 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1118 * For example, the "4bit ECC for each 512Byte" can be set with
1119 * NAND_ECC_INFO(4, 512).
1120 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1121 * reset. Should be deduced from timings described
1122 * in the datasheet.
1123 *
1124 */
1125 struct nand_flash_dev {
1126 char *name;
1127 union {
1128 struct {
1129 uint8_t mfr_id;
1130 uint8_t dev_id;
1131 };
1132 uint8_t id[NAND_MAX_ID_LEN];
1133 };
1134 unsigned int pagesize;
1135 unsigned int chipsize;
1136 unsigned int erasesize;
1137 unsigned int options;
1138 uint16_t id_len;
1139 uint16_t oobsize;
1140 struct {
1141 uint16_t strength_ds;
1142 uint16_t step_ds;
1143 } ecc;
1144 int onfi_timing_mode_default;
1145 };
1146
1147 /**
1148 * struct nand_manufacturer - NAND Flash Manufacturer ID Structure
1149 * @name: Manufacturer name
1150 * @id: manufacturer ID code of device.
1151 * @ops: manufacturer operations
1152 */
1153 struct nand_manufacturer {
1154 int id;
1155 char *name;
1156 const struct nand_manufacturer_ops *ops;
1157 };
1158
1159 extern struct nand_flash_dev nand_flash_ids[];
1160 extern struct nand_manufacturer nand_manuf_ids[];
1161
1162 extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops;
1163 extern const struct nand_manufacturer_ops samsung_nand_manuf_ops;
1164 extern const struct nand_manufacturer_ops hynix_nand_manuf_ops;
1165 extern const struct nand_manufacturer_ops micron_nand_manuf_ops;
1166 extern const struct nand_manufacturer_ops amd_nand_manuf_ops;
1167 extern const struct nand_manufacturer_ops macronix_nand_manuf_ops;
1168
1169 int nand_default_bbt(struct mtd_info *mtd);
1170 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1171 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1172 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1173 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1174 int allowbbt);
1175 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1176 size_t *retlen, uint8_t *buf);
1177
1178 /*
1179 * Constants for oob configuration
1180 */
1181 #define NAND_SMALL_BADBLOCK_POS 5
1182 #define NAND_LARGE_BADBLOCK_POS 0
1183
1184 /**
1185 * struct platform_nand_chip - chip level device structure
1186 * @nr_chips: max. number of chips to scan for
1187 * @chip_offset: chip number offset
1188 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1189 * @partitions: mtd partition list
1190 * @chip_delay: R/B delay value in us
1191 * @options: Option flags, e.g. 16bit buswidth
1192 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1193 * @part_probe_types: NULL-terminated array of probe types
1194 */
1195 struct platform_nand_chip {
1196 int nr_chips;
1197 int chip_offset;
1198 int nr_partitions;
1199 struct mtd_partition *partitions;
1200 int chip_delay;
1201 unsigned int options;
1202 unsigned int bbt_options;
1203 const char **part_probe_types;
1204 };
1205
1206 /* Keep gcc happy */
1207 struct platform_device;
1208
1209 /**
1210 * struct platform_nand_ctrl - controller level device structure
1211 * @probe: platform specific function to probe/setup hardware
1212 * @remove: platform specific function to remove/teardown hardware
1213 * @hwcontrol: platform specific hardware control structure
1214 * @dev_ready: platform specific function to read ready/busy pin
1215 * @select_chip: platform specific chip select function
1216 * @cmd_ctrl: platform specific function for controlling
1217 * ALE/CLE/nCE. Also used to write command and address
1218 * @write_buf: platform specific function for write buffer
1219 * @read_buf: platform specific function for read buffer
1220 * @read_byte: platform specific function to read one byte from chip
1221 * @priv: private data to transport driver specific settings
1222 *
1223 * All fields are optional and depend on the hardware driver requirements
1224 */
1225 struct platform_nand_ctrl {
1226 int (*probe)(struct platform_device *pdev);
1227 void (*remove)(struct platform_device *pdev);
1228 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1229 int (*dev_ready)(struct mtd_info *mtd);
1230 void (*select_chip)(struct mtd_info *mtd, int chip);
1231 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1232 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1233 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1234 unsigned char (*read_byte)(struct mtd_info *mtd);
1235 void *priv;
1236 };
1237
1238 /**
1239 * struct platform_nand_data - container structure for platform-specific data
1240 * @chip: chip level chip structure
1241 * @ctrl: controller level device structure
1242 */
1243 struct platform_nand_data {
1244 struct platform_nand_chip chip;
1245 struct platform_nand_ctrl ctrl;
1246 };
1247
1248 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
1249 /* return the supported features. */
onfi_feature(struct nand_chip * chip)1250 static inline int onfi_feature(struct nand_chip *chip)
1251 {
1252 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1253 }
1254
1255 /* return the supported asynchronous timing mode. */
onfi_get_async_timing_mode(struct nand_chip * chip)1256 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1257 {
1258 if (!chip->onfi_version)
1259 return ONFI_TIMING_MODE_UNKNOWN;
1260 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1261 }
1262
1263 /* return the supported synchronous timing mode. */
onfi_get_sync_timing_mode(struct nand_chip * chip)1264 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1265 {
1266 if (!chip->onfi_version)
1267 return ONFI_TIMING_MODE_UNKNOWN;
1268 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1269 }
1270 #else
onfi_feature(struct nand_chip * chip)1271 static inline int onfi_feature(struct nand_chip *chip)
1272 {
1273 return 0;
1274 }
1275
onfi_get_async_timing_mode(struct nand_chip * chip)1276 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1277 {
1278 return ONFI_TIMING_MODE_UNKNOWN;
1279 }
1280
onfi_get_sync_timing_mode(struct nand_chip * chip)1281 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1282 {
1283 return ONFI_TIMING_MODE_UNKNOWN;
1284 }
1285 #endif
1286
1287 int onfi_init_data_interface(struct nand_chip *chip,
1288 struct nand_data_interface *iface,
1289 enum nand_data_interface_type type,
1290 int timing_mode);
1291
1292 /*
1293 * Check if it is a SLC nand.
1294 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1295 * We do not distinguish the MLC and TLC now.
1296 */
nand_is_slc(struct nand_chip * chip)1297 static inline bool nand_is_slc(struct nand_chip *chip)
1298 {
1299 return chip->bits_per_cell == 1;
1300 }
1301
1302 /**
1303 * Check if the opcode's address should be sent only on the lower 8 bits
1304 * @command: opcode to check
1305 */
nand_opcode_8bits(unsigned int command)1306 static inline int nand_opcode_8bits(unsigned int command)
1307 {
1308 switch (command) {
1309 case NAND_CMD_READID:
1310 case NAND_CMD_PARAM:
1311 case NAND_CMD_GET_FEATURES:
1312 case NAND_CMD_SET_FEATURES:
1313 return 1;
1314 default:
1315 break;
1316 }
1317 return 0;
1318 }
1319
1320 /* return the supported JEDEC features. */
jedec_feature(struct nand_chip * chip)1321 static inline int jedec_feature(struct nand_chip *chip)
1322 {
1323 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1324 : 0;
1325 }
1326
1327 /* Standard NAND functions from nand_base.c */
1328 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1329 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1330 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1331 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1332 uint8_t nand_read_byte(struct mtd_info *mtd);
1333
1334 /* get timing characteristics from ONFI timing mode. */
1335 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1336 /* get data interface from ONFI timing mode 0, used after reset. */
1337 const struct nand_data_interface *nand_get_default_data_interface(void);
1338
1339 int nand_check_erased_ecc_chunk(void *data, int datalen,
1340 void *ecc, int ecclen,
1341 void *extraoob, int extraooblen,
1342 int threshold);
1343
1344 int nand_check_ecc_caps(struct nand_chip *chip,
1345 const struct nand_ecc_caps *caps, int oobavail);
1346
1347 int nand_match_ecc_req(struct nand_chip *chip,
1348 const struct nand_ecc_caps *caps, int oobavail);
1349
1350 int nand_maximize_ecc(struct nand_chip *chip,
1351 const struct nand_ecc_caps *caps, int oobavail);
1352
1353 /* Reset and initialize a NAND device */
1354 int nand_reset(struct nand_chip *chip, int chipnr);
1355
1356 /* NAND operation helpers */
1357 int nand_reset_op(struct nand_chip *chip);
1358 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1359 unsigned int len);
1360 int nand_status_op(struct nand_chip *chip, u8 *status);
1361 int nand_exit_status_op(struct nand_chip *chip);
1362 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1363 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1364 unsigned int offset_in_page, void *buf, unsigned int len);
1365 int nand_change_read_column_op(struct nand_chip *chip,
1366 unsigned int offset_in_page, void *buf,
1367 unsigned int len, bool force_8bit);
1368 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1369 unsigned int offset_in_page, void *buf, unsigned int len);
1370 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1371 unsigned int offset_in_page, const void *buf,
1372 unsigned int len);
1373 int nand_prog_page_end_op(struct nand_chip *chip);
1374 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1375 unsigned int offset_in_page, const void *buf,
1376 unsigned int len);
1377 int nand_change_write_column_op(struct nand_chip *chip,
1378 unsigned int offset_in_page, const void *buf,
1379 unsigned int len, bool force_8bit);
1380 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1381 bool force_8bit);
1382 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1383 unsigned int len, bool force_8bit);
1384
1385 /* Default extended ID decoding function */
1386 void nand_decode_ext_id(struct nand_chip *chip);
1387
1388 #endif /* __LINUX_MTD_RAWNAND_H */
1389