1 /* 2 * NS16550 Serial Port 3 * originally from linux source (arch/powerpc/boot/ns16550.h) 4 * 5 * Cleanup and unification 6 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH 7 * 8 * modified slightly to 9 * have addresses as offsets from CONFIG_SYS_ISA_BASE 10 * added a few more definitions 11 * added prototypes for ns16550.c 12 * reduced no of com ports to 2 13 * modifications (c) Rob Taylor, Flying Pig Systems. 2000. 14 * 15 * added support for port on 64-bit bus 16 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems 17 */ 18 19 /* 20 * Note that the following macro magic uses the fact that the compiler 21 * will not allocate storage for arrays of size 0 22 */ 23 24 #ifndef __ns16550_h 25 #define __ns16550_h 26 27 #include <linux/types.h> 28 #include <serial.h> 29 30 #if CONFIG_IS_ENABLED(DM_SERIAL) || defined(CONFIG_NS16550_DYNAMIC) || \ 31 defined(CONFIG_DEBUG_UART) 32 /* 33 * For driver model we always use one byte per register, and sort out the 34 * differences in the driver. In the case of CONFIG_NS16550_DYNAMIC we do 35 * similar, and CONFIG_DEBUG_UART is responsible for shifts in its own manner. 36 */ 37 #define UART_REG(x) unsigned char x 38 #else 39 #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) 40 #error "Please define NS16550 registers size." 41 #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) 42 #define UART_REG(x) \ 43 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ 44 unsigned char x; 45 #elif (CONFIG_SYS_NS16550_REG_SIZE < 0) 46 #define UART_REG(x) \ 47 unsigned char x; \ 48 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; 49 #endif 50 #endif /* CONFIG_NS16550_DYNAMIC */ 51 52 enum ns16550_flags { 53 NS16550_FLAG_IO = 1 << 0, /* Use I/O access (else mem-mapped) */ 54 NS16550_FLAG_ENDIAN = 1 << 1, /* Use out_le/be_32() */ 55 NS16550_FLAG_BE = 1 << 2, /* Big-endian access (else little) */ 56 }; 57 58 /** 59 * struct ns16550_plat - information about a NS16550 port 60 * 61 * @base: Base register address 62 * @size: Size of register area in bytes 63 * @reg_width: IO accesses size of registers (in bytes, 1 or 4) 64 * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) 65 * @reg_offset: Offset to start of registers (normally 0) 66 * @clock: UART base clock speed in Hz 67 * @fcr: Offset of FCR register (normally UART_FCR_DEFVAL) 68 * @flags: A few flags (enum ns16550_flags) 69 * @bdf: PCI slot/function (pci_dev_t) 70 */ 71 struct ns16550_plat { 72 ulong base; 73 ulong size; 74 int reg_width; 75 int reg_shift; 76 int reg_offset; 77 int clock; 78 u32 fcr; 79 int flags; 80 #if defined(CONFIG_PCI) && defined(CONFIG_SPL) 81 int bdf; 82 #endif 83 }; 84 85 struct udevice; 86 87 struct ns16550 { 88 UART_REG(rbr); /* 0 */ 89 UART_REG(ier); /* 1 */ 90 UART_REG(fcr); /* 2 */ 91 UART_REG(lcr); /* 3 */ 92 UART_REG(mcr); /* 4 */ 93 UART_REG(lsr); /* 5 */ 94 UART_REG(msr); /* 6 */ 95 UART_REG(spr); /* 7 */ 96 #ifdef CONFIG_SOC_DA8XX 97 UART_REG(reg8); /* 8 */ 98 UART_REG(reg9); /* 9 */ 99 UART_REG(revid1); /* A */ 100 UART_REG(revid2); /* B */ 101 UART_REG(pwr_mgmt); /* C */ 102 UART_REG(mdr1); /* D */ 103 #else 104 UART_REG(mdr1); /* 8 */ 105 UART_REG(reg9); /* 9 */ 106 UART_REG(regA); /* A */ 107 UART_REG(regB); /* B */ 108 UART_REG(regC); /* C */ 109 UART_REG(regD); /* D */ 110 UART_REG(regE); /* E */ 111 UART_REG(uasr); /* F */ 112 UART_REG(scr); /* 10*/ 113 UART_REG(ssr); /* 11*/ 114 #endif 115 #if CONFIG_IS_ENABLED(DM_SERIAL) 116 struct ns16550_plat *plat; 117 #endif 118 }; 119 120 #if CONFIG_IS_ENABLED(DM_SERIAL) 121 #define serial_out(value, addr) \ 122 ns16550_writeb(com_port, \ 123 (unsigned char *)(addr) - (unsigned char *)com_port, value) 124 #define serial_in(addr) \ 125 ns16550_readb(com_port, \ 126 (unsigned char *)(addr) - (unsigned char *)com_port) 127 #endif 128 129 #define thr rbr 130 #define iir fcr 131 #define dll rbr 132 #define dlm ier 133 134 /* 135 * These are the definitions for the FIFO Control Register 136 */ 137 #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ 138 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 139 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 140 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 141 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ 142 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ 143 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ 144 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ 145 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ 146 147 #define UART_FCR_RXSR 0x02 /* Receiver soft reset */ 148 #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ 149 150 /* Ingenic JZ47xx specific UART-enable bit. */ 151 #define UART_FCR_UME 0x10 152 153 /* Clear & enable FIFOs */ 154 #define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \ 155 UART_FCR_RXSR | \ 156 UART_FCR_TXSR) 157 158 /* 159 * These are the definitions for the Modem Control Register 160 */ 161 #define UART_MCR_DTR 0x01 /* DTR */ 162 #define UART_MCR_RTS 0x02 /* RTS */ 163 #define UART_MCR_OUT1 0x04 /* Out 1 */ 164 #define UART_MCR_OUT2 0x08 /* Out 2 */ 165 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 166 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ 167 168 #define UART_MCR_DMA_EN 0x04 169 #define UART_MCR_TX_DFR 0x08 170 171 /* 172 * These are the definitions for the Line Control Register 173 * 174 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 175 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 176 */ 177 #define UART_LCR_WLS_MSK 0x03 /* character length select mask */ 178 #define UART_LCR_WLS_5 0x00 /* 5 bit character length */ 179 #define UART_LCR_WLS_6 0x01 /* 6 bit character length */ 180 #define UART_LCR_WLS_7 0x02 /* 7 bit character length */ 181 #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ 182 #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ 183 #define UART_LCR_PEN 0x08 /* Parity eneble */ 184 #define UART_LCR_EPS 0x10 /* Even Parity Select */ 185 #define UART_LCR_STKP 0x20 /* Stick Parity */ 186 #define UART_LCR_SBRK 0x40 /* Set Break */ 187 #define UART_LCR_BKSE 0x80 /* Bank select enable */ 188 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 189 190 /* 191 * These are the definitions for the Line Status Register 192 */ 193 #define UART_LSR_DR 0x01 /* Data ready */ 194 #define UART_LSR_OE 0x02 /* Overrun */ 195 #define UART_LSR_PE 0x04 /* Parity error */ 196 #define UART_LSR_FE 0x08 /* Framing error */ 197 #define UART_LSR_BI 0x10 /* Break */ 198 #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ 199 #define UART_LSR_TEMT 0x40 /* Xmitter empty */ 200 #define UART_LSR_ERR 0x80 /* Error */ 201 202 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 203 #define UART_MSR_RI 0x40 /* Ring Indicator */ 204 #define UART_MSR_DSR 0x20 /* Data Set Ready */ 205 #define UART_MSR_CTS 0x10 /* Clear to Send */ 206 #define UART_MSR_DDCD 0x08 /* Delta DCD */ 207 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 208 #define UART_MSR_DDSR 0x02 /* Delta DSR */ 209 #define UART_MSR_DCTS 0x01 /* Delta CTS */ 210 211 /* 212 * These are the definitions for the Interrupt Identification Register 213 */ 214 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 215 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 216 217 #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 218 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 219 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 220 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 221 222 /* 223 * These are the definitions for the Interrupt Enable Register 224 */ 225 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 226 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 227 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 228 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 229 230 /* useful defaults for LCR */ 231 #define UART_LCR_8N1 0x03 232 233 void ns16550_init(struct ns16550 *com_port, int baud_divisor); 234 void ns16550_putc(struct ns16550 *com_port, char c); 235 char ns16550_getc(struct ns16550 *com_port); 236 int ns16550_tstc(struct ns16550 *com_port); 237 void ns16550_reinit(struct ns16550 *com_port, int baud_divisor); 238 int ns16550_serial_putc(struct udevice *dev, const char ch); 239 int ns16550_serial_pending(struct udevice *dev, bool input); 240 int ns16550_serial_getc(struct udevice *dev); 241 int ns16550_serial_setbrg(struct udevice *dev, int baudrate); 242 int ns16550_serial_setconfig(struct udevice *dev, uint serial_config); 243 int ns16550_serial_getinfo(struct udevice *dev, struct serial_device_info *info); 244 void ns16550_writeb(struct ns16550 *port, int offset, int value); 245 void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor); 246 247 /** 248 * ns16550_calc_divisor() - calculate the divisor given clock and baud rate 249 * 250 * Given the UART input clock and required baudrate, calculate the divisor 251 * that should be used. 252 * 253 * @port: UART port 254 * @clock: UART input clock speed in Hz 255 * @baudrate: Required baud rate 256 * Return: baud rate divisor that should be used 257 */ 258 int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate); 259 260 /** 261 * ns16550_serial_of_to_plat() - convert DT to platform data 262 * 263 * Decode a device tree node for an ns16550 device. This includes the 264 * register base address and register shift properties. The caller must set 265 * up the clock frequency. 266 * 267 * @dev: dev to decode platform data for 268 * @return: 0 if OK, -EINVAL on error 269 */ 270 int ns16550_serial_of_to_plat(struct udevice *dev); 271 272 /** 273 * ns16550_serial_probe() - probe a serial port 274 * 275 * This sets up the serial port ready for use, except for the baud rate 276 * Return: 0, or -ve on error 277 */ 278 int ns16550_serial_probe(struct udevice *dev); 279 280 /** 281 * struct ns16550_serial_ops - ns16550 serial operations 282 * 283 * These should be used by the client driver for the driver's 'ops' member 284 */ 285 extern const struct dm_serial_ops ns16550_serial_ops; 286 287 #endif /* __ns16550_h */ 288