1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Copyright (c) 2021 Maciej W. Rozycki <macro@orcam.me.uk>
9 */
10
11 #ifndef _PCI_H
12 #define _PCI_H
13
14 #define PCI_CFG_SPACE_SIZE 256
15 #define PCI_CFG_SPACE_EXP_SIZE 4096
16
17 /*
18 * Under PCI, each device has 256 bytes of configuration address space,
19 * of which the first 64 bytes are standardized as follows:
20 */
21 #define PCI_STD_HEADER_SIZEOF 64
22 #define PCI_VENDOR_ID 0x00 /* 16 bits */
23 #define PCI_DEVICE_ID 0x02 /* 16 bits */
24 #define PCI_COMMAND 0x04 /* 16 bits */
25 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
26 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
27 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
28 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
29 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
30 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
31 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
32 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
33 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
34 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
35
36 #define PCI_STATUS 0x06 /* 16 bits */
37 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
38 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
39 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
40 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
41 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
42 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
43 #define PCI_STATUS_DEVSEL_FAST 0x000
44 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
45 #define PCI_STATUS_DEVSEL_SLOW 0x400
46 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
47 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
48 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
49 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
50 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
51
52 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
53 revision */
54 #define PCI_REVISION_ID 0x08 /* Revision ID */
55 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
56 #define PCI_CLASS_DEVICE 0x0a /* Device class */
57 #define PCI_CLASS_CODE 0x0b /* Device class code */
58 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
59
60 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
61 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
62 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
63 #define PCI_HEADER_TYPE_NORMAL 0
64 #define PCI_HEADER_TYPE_BRIDGE 1
65 #define PCI_HEADER_TYPE_CARDBUS 2
66
67 #define PCI_BIST 0x0f /* 8 bits */
68 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
69 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
70 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
71
72 /*
73 * Base addresses specify locations in memory or I/O space.
74 * Decoded size can be determined by writing a value of
75 * 0xffffffff to the register, and reading it back. Only
76 * 1 bits are decoded.
77 */
78 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
79 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
80 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
81 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
82 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
83 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
84 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
85 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
86 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
87 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
88 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
89 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
90 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
91 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
92 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
93 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
94 /* bit 1 is reserved if address_space = 1 */
95
96 /* Convert a regsister address (e.g. PCI_BASE_ADDRESS_1) to a bar # (e.g. 1) */
97 #define pci_offset_to_barnum(offset) \
98 (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
99
100 /* Header type 0 (normal devices) */
101 #define PCI_CARDBUS_CIS 0x28
102 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
103 #define PCI_SUBSYSTEM_ID 0x2e
104 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
105 #define PCI_ROM_ADDRESS_ENABLE 0x01
106 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
107
108 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
109
110 /* 0x35-0x3b are reserved */
111 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
112 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
113 #define PCI_MIN_GNT 0x3e /* 8 bits */
114 #define PCI_MAX_LAT 0x3f /* 8 bits */
115
116 #define PCI_INTERRUPT_LINE_DISABLE 0xff
117
118 /* Header type 1 (PCI-to-PCI bridges) */
119 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
120 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
121 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
122 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
123 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
124 #define PCI_IO_LIMIT 0x1d
125 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
126 #define PCI_IO_RANGE_TYPE_16 0x00
127 #define PCI_IO_RANGE_TYPE_32 0x01
128 #define PCI_IO_RANGE_MASK ~0x0f
129 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
130 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
131 #define PCI_MEMORY_LIMIT 0x22
132 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
133 #define PCI_MEMORY_RANGE_MASK ~0x0f
134 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
135 #define PCI_PREF_MEMORY_LIMIT 0x26
136 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
137 #define PCI_PREF_RANGE_TYPE_32 0x00
138 #define PCI_PREF_RANGE_TYPE_64 0x01
139 #define PCI_PREF_RANGE_MASK ~0x0f
140 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
141 #define PCI_PREF_LIMIT_UPPER32 0x2c
142 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
143 #define PCI_IO_LIMIT_UPPER16 0x32
144 /* 0x34 same as for htype 0 */
145 /* 0x35-0x3b is reserved */
146 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
147 /* 0x3c-0x3d are same as for htype 0 */
148 #define PCI_BRIDGE_CONTROL 0x3e
149 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
150 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
151 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
152 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
153 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
154 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
155 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
156
157 /* Header type 2 (CardBus bridges) */
158 #define PCI_CB_CAPABILITY_LIST 0x14
159 /* 0x15 reserved */
160 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
161 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
162 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
163 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
164 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
165 #define PCI_CB_MEMORY_BASE_0 0x1c
166 #define PCI_CB_MEMORY_LIMIT_0 0x20
167 #define PCI_CB_MEMORY_BASE_1 0x24
168 #define PCI_CB_MEMORY_LIMIT_1 0x28
169 #define PCI_CB_IO_BASE_0 0x2c
170 #define PCI_CB_IO_BASE_0_HI 0x2e
171 #define PCI_CB_IO_LIMIT_0 0x30
172 #define PCI_CB_IO_LIMIT_0_HI 0x32
173 #define PCI_CB_IO_BASE_1 0x34
174 #define PCI_CB_IO_BASE_1_HI 0x36
175 #define PCI_CB_IO_LIMIT_1 0x38
176 #define PCI_CB_IO_LIMIT_1_HI 0x3a
177 #define PCI_CB_IO_RANGE_MASK ~0x03
178 /* 0x3c-0x3d are same as for htype 0 */
179 #define PCI_CB_BRIDGE_CONTROL 0x3e
180 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
181 #define PCI_CB_BRIDGE_CTL_SERR 0x02
182 #define PCI_CB_BRIDGE_CTL_ISA 0x04
183 #define PCI_CB_BRIDGE_CTL_VGA 0x08
184 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
185 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
186 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
187 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
188 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
189 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
190 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
191 #define PCI_CB_SUBSYSTEM_ID 0x42
192 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
193 /* 0x48-0x7f reserved */
194
195 /* Capability lists */
196
197 #define PCI_CAP_LIST_ID 0 /* Capability ID */
198 #define PCI_CAP_ID_PM 0x01 /* Power Management */
199 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
200 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
201 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
202 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
203 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
204 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
205 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */
206 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
207 #define PCI_CAP_ID_DBG 0x0A /* Debug port */
208 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
209 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
210 #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
211 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
212 #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
213 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
214 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
215 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
216 #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
217 #define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
218 #define PCI_CAP_ID_MAX PCI_CAP_ID_EA
219 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
220 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
221 #define PCI_CAP_SIZEOF 4
222
223 /* Power Management Registers */
224
225 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
226 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
227 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
228 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
229 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
230 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
231 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
232 #define PCI_PM_CTRL 4 /* PM control and status register */
233 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
234 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
235 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
236 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
237 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
238 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
239 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
240 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
241 #define PCI_PM_DATA_REGISTER 7 /* (??) */
242 #define PCI_PM_SIZEOF 8
243
244 /* AGP registers */
245
246 #define PCI_AGP_VERSION 2 /* BCD version number */
247 #define PCI_AGP_RFU 3 /* Rest of capability flags */
248 #define PCI_AGP_STATUS 4 /* Status register */
249 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
250 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
251 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
252 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
253 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
254 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
255 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
256 #define PCI_AGP_COMMAND 8 /* Control register */
257 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
258 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
259 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
260 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
261 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
262 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
263 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
264 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
265 #define PCI_AGP_SIZEOF 12
266
267 /* PCI-X registers */
268
269 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
270 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
271 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
272 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
273 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
274
275 /* Slot Identification */
276
277 #define PCI_SID_ESR 2 /* Expansion Slot Register */
278 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
279 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
280 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
281
282 /* Message Signalled Interrupts registers */
283
284 #define PCI_MSI_FLAGS 2 /* Various flags */
285 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
286 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
287 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
288 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
289 #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
290 #define PCI_MSI_RFU 3 /* Rest of capability flags */
291 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
292 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
293 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
294 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
295
296 #define PCI_MAX_PCI_DEVICES 32
297 #define PCI_MAX_PCI_FUNCTIONS 8
298
299 #define PCI_FIND_CAP_TTL 0x48
300 #define CAP_START_POS 0x40
301
302 /* Extended Capabilities (PCI-X 2.0 and Express) */
303 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
304 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
305 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
306
307 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
308 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
309 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
310 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
311 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
312 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
313 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
314 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
315 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
316 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
317 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
318 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
319 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
320 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
321 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
322 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
323 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
324 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
325 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
326 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
327 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
328 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
329 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
330 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
331 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
332 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
333 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
334 #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
335 #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
336 #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
337 #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
338
339 /* Enhanced Allocation Registers */
340 #define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */
341 #define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */
342 #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */
343 #define PCI_EA_ES 0x00000007 /* Entry Size */
344 #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
345 /* 9-14 map to VF BARs 0-5 respectively */
346 #define PCI_EA_BEI_VF_BAR0 9
347 #define PCI_EA_BEI_VF_BAR5 14
348 /* Base, MaxOffset registers */
349 /* bit 0 is reserved */
350 #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
351 #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
352
353 /* PCI Express capabilities */
354 #define PCI_EXP_FLAGS 2 /* Capabilities register */
355 #define PCI_EXP_FLAGS_VERS 0x000f /* Capability Version */
356 #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
357 #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
358 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
359 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
360 #define PCI_EXP_DEVCAP 4 /* Device capabilities */
361 #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
362 #define PCI_EXP_DEVCAP_PAYLOAD 0x0007 /* Max payload size supported */
363 #define PCI_EXP_DEVCAP_PAYLOAD_128B 0x0000 /* 128 Bytes */
364 #define PCI_EXP_DEVCAP_PAYLOAD_256B 0x0001 /* 256 Bytes */
365 #define PCI_EXP_DEVCAP_PAYLOAD_512B 0x0002 /* 512 Bytes */
366 #define PCI_EXP_DEVCAP_PAYLOAD_1024B 0x0003 /* 1024 Bytes */
367 #define PCI_EXP_DEVCAP_PAYLOAD_2048B 0x0004 /* 2048 Bytes */
368 #define PCI_EXP_DEVCAP_PAYLOAD_4096B 0x0005 /* 4096 Bytes */
369 #define PCI_EXP_DEVCTL 8 /* Device Control */
370 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
371 #define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */
372 #define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */
373 #define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */
374 #define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */
375 #define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */
376 #define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */
377 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
378 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
379 #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
380 #define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */
381 #define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */
382 #define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */
383 #define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
384 #define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */
385 #define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */
386 #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
387 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */
388 #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
389 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
390 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
391 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
392 #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
393 #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
394 #define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
395 #define PCI_EXP_LNKCAP_ASPM_L1 0x00000800 /* ASPM L1 Support */
396 #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
397 #define PCI_EXP_LNKCTL 16 /* Link Control */
398 #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */
399 #define PCI_EXP_LNKSTA 18 /* Link Status */
400 #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
401 #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
402 #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
403 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
404 #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
405 #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
406 #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
407 #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
408 #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
409 #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
410 #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
411 #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
412 #define PCI_EXP_RTCTL 28 /* Root Control */
413 #define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */
414 #define PCI_EXP_RTCAP 30 /* Root Capabilities */
415 #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
416 #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
417 #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */
418 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
419 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
420 #define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */
421 #define PCI_EXP_LNKCAP2_SLS 0x000000fe /* Supported Link Speeds Vector */
422 #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
423 #define PCI_EXP_LNKCTL2_TLS 0x000f /* Target Link Speed */
424 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Target Link Speed 2.5GT/s */
425 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Target Link Speed 5.0GT/s */
426 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Target Link Speed 8.0GT/s */
427
428 /* Advanced Error Reporting */
429 #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
430 #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
431 #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
432 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
433 #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
434 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
435
436 /* Single Root I/O Virtualization Registers */
437 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
438 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
439 #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
440 #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
441 #define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
442 #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
443 #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
444 #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
445 #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
446 #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
447 #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
448
449 /* Include the ID list */
450
451 #include <pci_ids.h>
452
453 /*
454 * Config Address for PCI Configuration Mechanism #1
455 *
456 * See PCI Local Bus Specification, Revision 3.0,
457 * Section 3.2.2.3.2, Figure 3-2, p. 50.
458 */
459
460 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
461 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
462 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
463
464 #define PCI_CONF1_BUS_MASK 0xff
465 #define PCI_CONF1_DEV_MASK 0x1f
466 #define PCI_CONF1_FUNC_MASK 0x7
467 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
468
469 #define PCI_CONF1_ENABLE BIT(31)
470 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
471 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
472 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
473 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
474
475 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
476 (PCI_CONF1_ENABLE | \
477 PCI_CONF1_BUS(bus) | \
478 PCI_CONF1_DEV(dev) | \
479 PCI_CONF1_FUNC(func) | \
480 PCI_CONF1_REG(reg))
481
482 /*
483 * Extension of PCI Config Address for accessing extended PCIe registers
484 *
485 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
486 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
487 * are used for specifying additional 4 high bits of PCI Express register.
488 */
489
490 #define PCI_CONF1_EXT_REG_SHIFT 16
491 #define PCI_CONF1_EXT_REG_MASK 0xf00
492 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
493
494 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
495 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
496 PCI_CONF1_EXT_REG(reg))
497
498 /*
499 * Enhanced Configuration Access Mechanism (ECAM)
500 *
501 * See PCI Express Base Specification, Revision 5.0, Version 1.0,
502 * Section 7.2.2, Table 7-1, p. 677.
503 */
504 #define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */
505 #define PCIE_ECAM_DEV_SHIFT 15 /* Device number */
506 #define PCIE_ECAM_FUNC_SHIFT 12 /* Function number */
507
508 #define PCIE_ECAM_BUS_MASK 0xff
509 #define PCIE_ECAM_DEV_MASK 0x1f
510 #define PCIE_ECAM_FUNC_MASK 0x7
511 #define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */
512
513 #define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT)
514 #define PCIE_ECAM_DEV(x) (((x) & PCIE_ECAM_DEV_MASK) << PCIE_ECAM_DEV_SHIFT)
515 #define PCIE_ECAM_FUNC(x) (((x) & PCIE_ECAM_FUNC_MASK) << PCIE_ECAM_FUNC_SHIFT)
516 #define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK)
517
518 #define PCIE_ECAM_OFFSET(bus, dev, func, where) \
519 (PCIE_ECAM_BUS(bus) | \
520 PCIE_ECAM_DEV(dev) | \
521 PCIE_ECAM_FUNC(func) | \
522 PCIE_ECAM_REG(where))
523
524 #ifndef __ASSEMBLY__
525
526 #include <linux/types.h>
527 #include <dm/pci.h>
528
529 #ifdef CONFIG_SYS_PCI_64BIT
530 typedef u64 pci_addr_t;
531 typedef u64 pci_size_t;
532 #else
533 typedef unsigned long pci_addr_t;
534 typedef unsigned long pci_size_t;
535 #endif
536
537 struct pci_region {
538 pci_addr_t bus_start; /* Start on the bus */
539 phys_addr_t phys_start; /* Start in physical address space */
540 pci_size_t size; /* Size */
541 unsigned long flags; /* Resource flags */
542
543 pci_addr_t bus_lower;
544 };
545
546 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */
547 #define PCI_REGION_IO 0x00000001 /* PCI IO space */
548 #define PCI_REGION_TYPE 0x00000001
549 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
550
551 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
552 #define PCI_REGION_RO 0x00000200 /* Read-only memory */
553
pci_set_region(struct pci_region * reg,pci_addr_t bus_start,phys_addr_t phys_start,pci_size_t size,unsigned long flags)554 static inline void pci_set_region(struct pci_region *reg,
555 pci_addr_t bus_start,
556 phys_addr_t phys_start,
557 pci_size_t size,
558 unsigned long flags) {
559 reg->bus_start = bus_start;
560 reg->phys_start = phys_start;
561 reg->size = size;
562 reg->flags = flags;
563 }
564
565 typedef int pci_dev_t;
566
567 #define PCI_BUS(d) (((d) >> 16) & 0xff)
568
569 /*
570 * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot
571 * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0.
572 * Please see the Linux header include/uapi/linux/pci.h for more details.
573 * This is relevant for the following macros:
574 * PCI_DEV, PCI_FUNC, PCI_DEVFN
575 * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with
576 * the remark from above (input is in bits 15-8 instead of 7-0.
577 */
578 #define PCI_DEV(d) (((d) >> 11) & 0x1f)
579 #define PCI_FUNC(d) (((d) >> 8) & 0x7)
580 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
581
582 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
583 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
584 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
585 #define PCI_ANY_ID (~0)
586
587 /* Convert from Linux format to U-Boot format */
588 #define PCI_TO_BDF(val) ((val) << 8)
589
590 struct pci_device_id {
591 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
592 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
593 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
594 unsigned long driver_data; /* Data private to the driver */
595 };
596
597 struct pci_controller;
598
599 struct pci_config_table {
600 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
601 unsigned int class; /* Class ID, or PCI_ANY_ID */
602 unsigned int bus; /* Bus number, or PCI_ANY_ID */
603 unsigned int dev; /* Device number, or PCI_ANY_ID */
604 unsigned int func; /* Function number, or PCI_ANY_ID */
605
606 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
607 struct pci_config_table *);
608 unsigned long priv[3];
609 };
610
611 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
612 struct pci_config_table *);
613 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
614 struct pci_config_table *);
615
616 #define INDIRECT_TYPE_NO_PCIE_LINK 1
617
618 /**
619 * Structure of a PCI controller (host bridge)
620 *
621 * With driver model this is dev_get_uclass_priv(bus)
622 *
623 * @skip_auto_config_until_reloc: true to avoid auto-config until U-Boot has
624 * relocated. Normally if PCI is used before relocation, this happens
625 * before relocation also. Some platforms set up static configuration in
626 * TPL/SPL to reduce code size and boot time, since these phases only know
627 * about a small subset of PCI devices. This is normally false.
628 */
629 struct pci_controller {
630 struct udevice *bus;
631 struct udevice *ctlr;
632 bool skip_auto_config_until_reloc;
633
634 int first_busno;
635 int last_busno;
636
637 volatile unsigned int *cfg_addr;
638 volatile unsigned char *cfg_data;
639
640 int indirect_type;
641
642 /*
643 * TODO(sjg@chromium.org): With driver model we use struct
644 * pci_controller for both the controller and any bridge devices
645 * attached to it. But there is only one region list and it is in the
646 * top-level controller.
647 *
648 * This could be changed so that struct pci_controller is only used
649 * for PCI controllers and a separate UCLASS (or perhaps
650 * UCLASS_PCI_GENERIC) is used for bridges.
651 */
652 struct pci_region *regions;
653 int region_count;
654
655 struct pci_config_table *config_table;
656
657 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
658
659 /* Used by auto config */
660 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
661 };
662
663 #if defined(CONFIG_DM_PCI_COMPAT)
664 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
665 pci_addr_t addr, unsigned long flags);
666 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
667 phys_addr_t addr, unsigned long flags);
668
669 #define pci_phys_to_bus(dev, addr, flags) \
670 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
671 #define pci_bus_to_phys(dev, addr, flags) \
672 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
673
674 #define pci_virt_to_bus(dev, addr, flags) \
675 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
676 (virt_to_phys(addr)), (flags))
677 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
678 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
679 (addr), (flags)), \
680 (len), (map_flags))
681
682 #define pci_phys_to_mem(dev, addr) \
683 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
684 #define pci_mem_to_phys(dev, addr) \
685 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
686 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
687 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
688
689 #define pci_virt_to_mem(dev, addr) \
690 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
691 #define pci_mem_to_virt(dev, addr, len, map_flags) \
692 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
693 #define pci_virt_to_io(dev, addr) \
694 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
695 #define pci_io_to_virt(dev, addr, len, map_flags) \
696 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
697
698 /* For driver model these are defined in macros in pci_compat.c */
699 extern int pci_hose_read_config_byte(struct pci_controller *hose,
700 pci_dev_t dev, int where, u8 *val);
701 extern int pci_hose_read_config_word(struct pci_controller *hose,
702 pci_dev_t dev, int where, u16 *val);
703 extern int pci_hose_read_config_dword(struct pci_controller *hose,
704 pci_dev_t dev, int where, u32 *val);
705 extern int pci_hose_write_config_byte(struct pci_controller *hose,
706 pci_dev_t dev, int where, u8 val);
707 extern int pci_hose_write_config_word(struct pci_controller *hose,
708 pci_dev_t dev, int where, u16 val);
709 extern int pci_hose_write_config_dword(struct pci_controller *hose,
710 pci_dev_t dev, int where, u32 val);
711 #endif
712
713 void pciauto_region_init(struct pci_region *res);
714 void pciauto_region_align(struct pci_region *res, pci_size_t size);
715 void pciauto_config_init(struct pci_controller *hose);
716
717 /**
718 * pciauto_region_allocate() - Allocate resources from a PCI resource region
719 *
720 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
721 * false, the result will be guaranteed to fit in 32 bits.
722 *
723 * @res: PCI region to allocate from
724 * @size: Amount of bytes to allocate
725 * @bar: Returns the PCI bus address of the allocated resource
726 * @supports_64bit: Whether to allow allocations above the 32-bit boundary
727 * Return: 0 if successful, -1 on failure
728 */
729 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
730 pci_addr_t *bar, bool supports_64bit);
731 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
732
733 #if defined(CONFIG_DM_PCI_COMPAT)
734 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
735 pci_dev_t dev, int where, u8 *val);
736 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
737 pci_dev_t dev, int where, u16 *val);
738 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
739 pci_dev_t dev, int where, u8 val);
740 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
741 pci_dev_t dev, int where, u16 val);
742
743 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
744 extern void pci_register_hose(struct pci_controller* hose);
745 extern struct pci_controller* pci_bus_to_hose(int bus);
746 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
747 extern struct pci_controller *pci_get_hose_head(void);
748
749 extern int pci_hose_scan(struct pci_controller *hose);
750 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
751
752 extern void pciauto_setup_device(struct pci_controller *hose,
753 pci_dev_t dev, int bars_num,
754 struct pci_region *mem,
755 struct pci_region *prefetch,
756 struct pci_region *io);
757 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
758 pci_dev_t dev, int sub_bus);
759 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
760 pci_dev_t dev, int sub_bus);
761 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
762
763 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
764 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
765 pci_dev_t pci_find_class(unsigned int find_class, int index);
766
767 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
768 int cap);
769 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
770 u8 hdr_type);
771 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
772 int cap);
773
774 int pci_find_next_ext_capability(struct pci_controller *hose,
775 pci_dev_t dev, int start, int cap);
776 int pci_hose_find_ext_capability(struct pci_controller *hose,
777 pci_dev_t dev, int cap);
778
779 #endif /* defined(CONFIG_DM_PCI_COMPAT) */
780
781 const char * pci_class_str(u8 class);
782 int pci_last_busno(void);
783
784 #ifdef CONFIG_MPC85xx
785 extern void pci_mpc85xx_init (struct pci_controller *hose);
786 #endif
787
788 /**
789 * pci_write_bar32() - Write the address of a BAR including control bits
790 *
791 * This writes a raw address (with control bits) to a bar. This can be used
792 * with devices which require hard-coded addresses, not part of the normal
793 * PCI enumeration process.
794 *
795 * This is only available if CONFIG_DM_PCI_COMPAT is enabled
796 *
797 * @hose: PCI hose to use
798 * @dev: PCI device to update
799 * @barnum: BAR number (0-5)
800 * @addr: BAR address with control bits
801 */
802 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
803 u32 addr);
804
805 /**
806 * pci_read_bar32() - read the address of a bar
807 *
808 * This is only available if CONFIG_DM_PCI_COMPAT is enabled
809 *
810 * @hose: PCI hose to use
811 * @dev: PCI device to inspect
812 * @barnum: BAR number (0-5)
813 * Return: address of the bar, masking out any control bits
814 * */
815 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
816
817 /**
818 * pci_hose_find_devices() - Find devices by vendor/device ID
819 *
820 * This is only available if CONFIG_DM_PCI_COMPAT is enabled
821 *
822 * @hose: PCI hose to search
823 * @busnum: Bus number to search
824 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
825 * @indexp: Pointer to device index to find. To find the first matching
826 * device, pass 0; to find the second, pass 1, etc. This
827 * parameter is decremented for each non-matching device so
828 * can be called repeatedly.
829 */
830 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
831 struct pci_device_id *ids, int *indexp);
832
833 /* Access sizes for PCI reads and writes */
834 enum pci_size_t {
835 PCI_SIZE_8,
836 PCI_SIZE_16,
837 PCI_SIZE_32,
838 };
839
840 struct udevice;
841
842 /**
843 * struct pci_child_plat - information stored about each PCI device
844 *
845 * Every device on a PCI bus has this per-child data.
846 *
847 * It can be accessed using dev_get_parent_plat(dev) if dev->parent is a
848 * PCI bus (i.e. UCLASS_PCI)
849 *
850 * @devfn: Encoded device and function index - see PCI_DEVFN()
851 * @vendor: PCI vendor ID (see pci_ids.h)
852 * @device: PCI device ID (see pci_ids.h)
853 * @class: PCI class, 3 bytes: (base, sub, prog-if)
854 * @is_virtfn: True for Virtual Function device
855 * @pfdev: Handle to Physical Function device
856 * @virtid: Virtual Function Index
857 */
858 struct pci_child_plat {
859 int devfn;
860 unsigned short vendor;
861 unsigned short device;
862 unsigned int class;
863
864 /* Variables for CONFIG_PCI_SRIOV */
865 bool is_virtfn;
866 struct udevice *pfdev;
867 int virtid;
868 };
869
870 /* PCI bus operations */
871 struct dm_pci_ops {
872 /**
873 * read_config() - Read a PCI configuration value
874 *
875 * PCI buses must support reading and writing configuration values
876 * so that the bus can be scanned and its devices configured.
877 *
878 * Normally PCI_BUS(@bdf) is the same as @dev_seq(bus), but not always.
879 * If bridges exist it is possible to use the top-level bus to
880 * access a sub-bus. In that case @bus will be the top-level bus
881 * and PCI_BUS(bdf) will be a different (higher) value
882 *
883 * @bus: Bus to read from
884 * @bdf: Bus, device and function to read
885 * @offset: Byte offset within the device's configuration space
886 * @valuep: Place to put the returned value
887 * @size: Access size
888 * @return 0 if OK, -ve on error
889 */
890 int (*read_config)(const struct udevice *bus, pci_dev_t bdf,
891 uint offset, ulong *valuep, enum pci_size_t size);
892 /**
893 * write_config() - Write a PCI configuration value
894 *
895 * @bus: Bus to write to
896 * @bdf: Bus, device and function to write
897 * @offset: Byte offset within the device's configuration space
898 * @value: Value to write
899 * @size: Access size
900 * @return 0 if OK, -ve on error
901 */
902 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
903 ulong value, enum pci_size_t size);
904 };
905
906 /* Get access to a PCI bus' operations */
907 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
908
909 /**
910 * dm_pci_get_bdf() - Get the BDF value for a device
911 *
912 * @dev: Device to check
913 * Return: bus/device/function value (see PCI_BDF())
914 */
915 pci_dev_t dm_pci_get_bdf(const struct udevice *dev);
916
917 /**
918 * pci_bind_bus_devices() - scan a PCI bus and bind devices
919 *
920 * Scan a PCI bus looking for devices. Bind each one that is found. If
921 * devices are already bound that match the scanned devices, just update the
922 * child data so that the device can be used correctly (this happens when
923 * the device tree describes devices we expect to see on the bus).
924 *
925 * Devices that are bound in this way will use a generic PCI driver which
926 * does nothing. The device can still be accessed but will not provide any
927 * driver interface.
928 *
929 * @bus: Bus containing devices to bind
930 * Return: 0 if OK, -ve on error
931 */
932 int pci_bind_bus_devices(struct udevice *bus);
933
934 /**
935 * pci_auto_config_devices() - configure bus devices ready for use
936 *
937 * This works through all devices on a bus by scanning the driver model
938 * data structures (normally these have been set up by pci_bind_bus_devices()
939 * earlier).
940 *
941 * Space is allocated for each PCI base address register (BAR) so that the
942 * devices are mapped into memory and I/O space ready for use.
943 *
944 * @bus: Bus containing devices to bind
945 * Return: 0 if OK, -ve on error
946 */
947 int pci_auto_config_devices(struct udevice *bus);
948
949 /**
950 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
951 *
952 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
953 * @devp: Returns the device for this address, if found
954 * Return: 0 if OK, -ENODEV if not found
955 */
956 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
957
958 /**
959 * pci_bus_find_devfn() - Find a device on a bus
960 *
961 * @find_devfn: PCI device address (device and function only)
962 * @devp: Returns the device for this address, if found
963 * Return: 0 if OK, -ENODEV if not found
964 */
965 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
966 struct udevice **devp);
967
968 /**
969 * pci_find_first_device() - return the first available PCI device
970 *
971 * This function and pci_find_next_device() allow iteration through all
972 * available PCI devices on all buses. Assuming there are any, this will
973 * return the first one.
974 *
975 * @devp: Set to the first available device, or NULL if no more are left
976 * or we got an error
977 * Return: 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
978 */
979 int pci_find_first_device(struct udevice **devp);
980
981 /**
982 * pci_find_next_device() - return the next available PCI device
983 *
984 * Finds the next available PCI device after the one supplied, or sets @devp
985 * to NULL if there are no more.
986 *
987 * @devp: On entry, the last device returned. Set to the next available
988 * device, or NULL if no more are left or we got an error
989 * Return: 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
990 */
991 int pci_find_next_device(struct udevice **devp);
992
993 /**
994 * pci_get_ff() - Returns a mask for the given access size
995 *
996 * @size: Access size
997 * Return: 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
998 * PCI_SIZE_32
999 */
1000 int pci_get_ff(enum pci_size_t size);
1001
1002 /**
1003 * pci_bus_find_devices () - Find devices on a bus
1004 *
1005 * @bus: Bus to search
1006 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
1007 * @indexp: Pointer to device index to find. To find the first matching
1008 * device, pass 0; to find the second, pass 1, etc. This
1009 * parameter is decremented for each non-matching device so
1010 * can be called repeatedly.
1011 * @devp: Returns matching device if found
1012 * Return: 0 if found, -ENODEV if not
1013 */
1014 int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
1015 int *indexp, struct udevice **devp);
1016
1017 /**
1018 * pci_find_device_id() - Find a device on any bus
1019 *
1020 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
1021 * @index: Index number of device to find, 0 for the first match, 1 for
1022 * the second, etc.
1023 * @devp: Returns matching device if found
1024 * Return: 0 if found, -ENODEV if not
1025 */
1026 int pci_find_device_id(const struct pci_device_id *ids, int index,
1027 struct udevice **devp);
1028
1029 /**
1030 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
1031 *
1032 * This probes the given bus which causes it to be scanned for devices. The
1033 * devices will be bound but not probed.
1034 *
1035 * @hose specifies the PCI hose that will be used for the scan. This is
1036 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
1037 * in @bdf, and is a subordinate bus reachable from @hose.
1038 *
1039 * @hose: PCI hose to scan
1040 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
1041 * Return: 0 if OK, -ve on error
1042 */
1043 int dm_pci_hose_probe_bus(struct udevice *bus);
1044
1045 /**
1046 * pci_bus_read_config() - Read a configuration value from a device
1047 *
1048 * TODO(sjg@chromium.org): We should be able to pass just a device and have
1049 * it do the right thing. It would be good to have that function also.
1050 *
1051 * @bus: Bus to read from
1052 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1053 * @offset: Register offset to read
1054 * @valuep: Place to put the returned value
1055 * @size: Access size
1056 * Return: 0 if OK, -ve on error
1057 */
1058 int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
1059 unsigned long *valuep, enum pci_size_t size);
1060
1061 /**
1062 * pci_bus_write_config() - Write a configuration value to a device
1063 *
1064 * @bus: Bus to write from
1065 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1066 * @offset: Register offset to write
1067 * @value: Value to write
1068 * @size: Access size
1069 * Return: 0 if OK, -ve on error
1070 */
1071 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1072 unsigned long value, enum pci_size_t size);
1073
1074 /**
1075 * pci_bus_clrset_config32() - Update a configuration value for a device
1076 *
1077 * The register at @offset is updated to (oldvalue & ~clr) | set.
1078 *
1079 * @bus: Bus to access
1080 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1081 * @offset: Register offset to update
1082 * @clr: Bits to clear
1083 * @set: Bits to set
1084 * Return: 0 if OK, -ve on error
1085 */
1086 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1087 u32 clr, u32 set);
1088
1089 /**
1090 * Driver model PCI config access functions. Use these in preference to others
1091 * when you have a valid device
1092 */
1093 int dm_pci_read_config(const struct udevice *dev, int offset,
1094 unsigned long *valuep, enum pci_size_t size);
1095
1096 int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep);
1097 int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep);
1098 int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep);
1099
1100 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1101 enum pci_size_t size);
1102
1103 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1104 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1105 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
1106
1107 /**
1108 * These permit convenient read/modify/write on PCI configuration. The
1109 * register is updated to (oldvalue & ~clr) | set.
1110 */
1111 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1112 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1113 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
1114
1115 /*
1116 * The following functions provide access to the above without needing the
1117 * size parameter. We are trying to encourage the use of the 8/16/32-style
1118 * functions, rather than byte/word/dword. But both are supported.
1119 */
1120 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
1121 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1122 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1123 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1124 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1125 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
1126
1127 /**
1128 * pci_generic_mmap_write_config() - Generic helper for writing to
1129 * memory-mapped PCI configuration space.
1130 * @bus: Pointer to the PCI bus
1131 * @addr_f: Callback for calculating the config space address
1132 * @bdf: Identifies the PCI device to access
1133 * @offset: The offset into the device's configuration space
1134 * @value: The value to write
1135 * @size: Indicates the size of access to perform
1136 *
1137 * Write the value @value of size @size from offset @offset within the
1138 * configuration space of the device identified by the bus, device & function
1139 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
1140 * responsible for calculating the CPU address of the respective configuration
1141 * space offset.
1142 *
1143 * Return: 0 on success, else -EINVAL
1144 */
1145 int pci_generic_mmap_write_config(
1146 const struct udevice *bus,
1147 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
1148 void **addrp),
1149 pci_dev_t bdf,
1150 uint offset,
1151 ulong value,
1152 enum pci_size_t size);
1153
1154 /**
1155 * pci_generic_mmap_read_config() - Generic helper for reading from
1156 * memory-mapped PCI configuration space.
1157 * @bus: Pointer to the PCI bus
1158 * @addr_f: Callback for calculating the config space address
1159 * @bdf: Identifies the PCI device to access
1160 * @offset: The offset into the device's configuration space
1161 * @valuep: A pointer at which to store the read value
1162 * @size: Indicates the size of access to perform
1163 *
1164 * Read a value of size @size from offset @offset within the configuration
1165 * space of the device identified by the bus, device & function numbers in @bdf
1166 * on the PCI bus @bus. The callback function @addr_f is responsible for
1167 * calculating the CPU address of the respective configuration space offset.
1168 *
1169 * Return: 0 on success, else -EINVAL
1170 */
1171 int pci_generic_mmap_read_config(
1172 const struct udevice *bus,
1173 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
1174 void **addrp),
1175 pci_dev_t bdf,
1176 uint offset,
1177 ulong *valuep,
1178 enum pci_size_t size);
1179
1180 #if defined(CONFIG_PCI_SRIOV)
1181 /**
1182 * pci_sriov_init() - Scan Virtual Function devices
1183 *
1184 * @pdev: Physical Function udevice handle
1185 * @vf_en: Number of Virtual Function devices to enable
1186 * Return: 0 on success, -ve on error
1187 */
1188 int pci_sriov_init(struct udevice *pdev, int vf_en);
1189
1190 /**
1191 * pci_sriov_get_totalvfs() - Get total available Virtual Function devices
1192 *
1193 * @pdev: Physical Function udevice handle
1194 * Return: count on success, -ve on error
1195 */
1196 int pci_sriov_get_totalvfs(struct udevice *pdev);
1197 #endif
1198
1199 #ifdef CONFIG_DM_PCI_COMPAT
1200 /* Compatibility with old naming */
pci_write_config_dword(pci_dev_t pcidev,int offset,u32 value)1201 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1202 u32 value)
1203 {
1204 return pci_write_config32(pcidev, offset, value);
1205 }
1206
1207 /* Compatibility with old naming */
pci_write_config_word(pci_dev_t pcidev,int offset,u16 value)1208 static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1209 u16 value)
1210 {
1211 return pci_write_config16(pcidev, offset, value);
1212 }
1213
1214 /* Compatibility with old naming */
pci_write_config_byte(pci_dev_t pcidev,int offset,u8 value)1215 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1216 u8 value)
1217 {
1218 return pci_write_config8(pcidev, offset, value);
1219 }
1220
1221 /* Compatibility with old naming */
pci_read_config_dword(pci_dev_t pcidev,int offset,u32 * valuep)1222 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1223 u32 *valuep)
1224 {
1225 return pci_read_config32(pcidev, offset, valuep);
1226 }
1227
1228 /* Compatibility with old naming */
pci_read_config_word(pci_dev_t pcidev,int offset,u16 * valuep)1229 static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1230 u16 *valuep)
1231 {
1232 return pci_read_config16(pcidev, offset, valuep);
1233 }
1234
1235 /* Compatibility with old naming */
pci_read_config_byte(pci_dev_t pcidev,int offset,u8 * valuep)1236 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1237 u8 *valuep)
1238 {
1239 return pci_read_config8(pcidev, offset, valuep);
1240 }
1241 #endif /* CONFIG_DM_PCI_COMPAT */
1242
1243 /**
1244 * dm_pciauto_config_device() - configure a device ready for use
1245 *
1246 * Space is allocated for each PCI base address register (BAR) so that the
1247 * devices are mapped into memory and I/O space ready for use.
1248 *
1249 * @dev: Device to configure
1250 * Return: 0 if OK, -ve on error
1251 */
1252 int dm_pciauto_config_device(struct udevice *dev);
1253
1254 /**
1255 * pci_conv_32_to_size() - convert a 32-bit read value to the given size
1256 *
1257 * Some PCI buses must always perform 32-bit reads. The data must then be
1258 * shifted and masked to reflect the required access size and offset. This
1259 * function performs this transformation.
1260 *
1261 * @value: Value to transform (32-bit value read from @offset & ~3)
1262 * @offset: Register offset that was read
1263 * @size: Required size of the result
1264 * Return: the value that would have been obtained if the read had been
1265 * performed at the given offset with the correct size
1266 */
1267 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
1268
1269 /**
1270 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
1271 *
1272 * Some PCI buses must always perform 32-bit writes. To emulate a smaller
1273 * write the old 32-bit data must be read, updated with the required new data
1274 * and written back as a 32-bit value. This function performs the
1275 * transformation from the old value to the new value.
1276 *
1277 * @value: Value to transform (32-bit value read from @offset & ~3)
1278 * @offset: Register offset that should be written
1279 * @size: Required size of the write
1280 * Return: the value that should be written as a 32-bit access to @offset & ~3.
1281 */
1282 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1283 enum pci_size_t size);
1284
1285 /**
1286 * pci_get_controller() - obtain the controller to use for a bus
1287 *
1288 * @dev: Device to check
1289 * Return: pointer to the controller device for this bus
1290 */
1291 struct udevice *pci_get_controller(struct udevice *dev);
1292
1293 /**
1294 * pci_get_regions() - obtain pointers to all the region types
1295 *
1296 * @dev: Device to check
1297 * @iop: Returns a pointer to the I/O region, or NULL if none
1298 * @memp: Returns a pointer to the memory region, or NULL if none
1299 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
1300 * Return: the number of non-NULL regions returned, normally 3
1301 */
1302 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1303 struct pci_region **memp, struct pci_region **prefp);
1304 int
1305 pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index);
1306 /**
1307 * dm_pci_write_bar32() - Write the address of a BAR
1308 *
1309 * This writes a raw address to a bar
1310 *
1311 * @dev: PCI device to update
1312 * @barnum: BAR number (0-5)
1313 * @addr: BAR address
1314 */
1315 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1316
1317 /**
1318 * dm_pci_read_bar32() - read a base address register from a device
1319 *
1320 * @dev: Device to check
1321 * @barnum: Bar number to read (numbered from 0)
1322 * @return: value of BAR
1323 */
1324 u32 dm_pci_read_bar32(const struct udevice *dev, int barnum);
1325
1326 /**
1327 * dm_pci_bus_to_phys() - convert a PCI bus address range to a physical address
1328 *
1329 * @dev: Device containing the PCI address
1330 * @addr: PCI address to convert
1331 * @len: Length of the address range
1332 * @mask: Mask to match flags for the region type
1333 * @flags: Flags for the region type (PCI_REGION_...)
1334 * Return: physical address corresponding to that PCI bus address
1335 */
1336 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, size_t len,
1337 unsigned long mask, unsigned long flags);
1338
1339 /**
1340 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
1341 *
1342 * @dev: Device containing the bus address
1343 * @addr: Physical address to convert
1344 * @len: Length of the address range
1345 * @mask: Mask to match flags for the region type
1346 * @flags: Flags for the region type (PCI_REGION_...)
1347 * Return: PCI bus address corresponding to that physical address
1348 */
1349 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, size_t len,
1350 unsigned long mask, unsigned long flags);
1351
1352 /**
1353 * dm_pci_map_bar() - get a virtual address associated with a BAR region
1354 *
1355 * Looks up a base address register and finds the physical memory address
1356 * that corresponds to it.
1357 * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
1358 * type 1 functions.
1359 * Can also be used on type 0 functions that support Enhanced Allocation for
1360 * 32b/64b BARs. Note that duplicate BEI entries are not supported.
1361 * Can also be used on 64b bars on type 0 functions.
1362 *
1363 * @dev: Device to check
1364 * @bar: Bar register offset (PCI_BASE_ADDRESS_...)
1365 * @offset: Offset from the base to map
1366 * @len: Length to map
1367 * @mask: Mask to match flags for the region type
1368 * @flags: Flags for the region type (PCI_REGION_...)
1369 * @return: pointer to the virtual address to use or 0 on error
1370 */
1371 void *dm_pci_map_bar(struct udevice *dev, int bar, size_t offset, size_t len,
1372 unsigned long mask, unsigned long flags);
1373
1374 /**
1375 * dm_pci_find_next_capability() - find a capability starting from an offset
1376 *
1377 * Tell if a device supports a given PCI capability. Returns the
1378 * address of the requested capability structure within the device's
1379 * PCI configuration space or 0 in case the device does not support it.
1380 *
1381 * Possible values for @cap:
1382 *
1383 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1384 * %PCI_CAP_ID_PCIX PCI-X
1385 * %PCI_CAP_ID_EXP PCI Express
1386 * %PCI_CAP_ID_MSIX MSI-X
1387 *
1388 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1389 *
1390 * @dev: PCI device to query
1391 * @start: offset to start from
1392 * @cap: capability code
1393 * @return: capability address or 0 if not supported
1394 */
1395 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
1396
1397 /**
1398 * dm_pci_find_capability() - find a capability
1399 *
1400 * Tell if a device supports a given PCI capability. Returns the
1401 * address of the requested capability structure within the device's
1402 * PCI configuration space or 0 in case the device does not support it.
1403 *
1404 * Possible values for @cap:
1405 *
1406 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1407 * %PCI_CAP_ID_PCIX PCI-X
1408 * %PCI_CAP_ID_EXP PCI Express
1409 * %PCI_CAP_ID_MSIX MSI-X
1410 *
1411 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1412 *
1413 * @dev: PCI device to query
1414 * @cap: capability code
1415 * @return: capability address or 0 if not supported
1416 */
1417 int dm_pci_find_capability(struct udevice *dev, int cap);
1418
1419 /**
1420 * dm_pci_find_next_ext_capability() - find an extended capability
1421 * starting from an offset
1422 *
1423 * Tell if a device supports a given PCI express extended capability.
1424 * Returns the address of the requested extended capability structure
1425 * within the device's PCI configuration space or 0 in case the device
1426 * does not support it.
1427 *
1428 * Possible values for @cap:
1429 *
1430 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1431 * %PCI_EXT_CAP_ID_VC Virtual Channel
1432 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1433 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1434 *
1435 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1436 *
1437 * @dev: PCI device to query
1438 * @start: offset to start from
1439 * @cap: extended capability code
1440 * @return: extended capability address or 0 if not supported
1441 */
1442 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
1443
1444 /**
1445 * dm_pci_find_ext_capability() - find an extended capability
1446 *
1447 * Tell if a device supports a given PCI express extended capability.
1448 * Returns the address of the requested extended capability structure
1449 * within the device's PCI configuration space or 0 in case the device
1450 * does not support it.
1451 *
1452 * Possible values for @cap:
1453 *
1454 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1455 * %PCI_EXT_CAP_ID_VC Virtual Channel
1456 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1457 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1458 *
1459 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1460 *
1461 * @dev: PCI device to query
1462 * @cap: extended capability code
1463 * @return: extended capability address or 0 if not supported
1464 */
1465 int dm_pci_find_ext_capability(struct udevice *dev, int cap);
1466
1467 /**
1468 * dm_pci_flr() - Perform FLR if the device suppoorts it
1469 *
1470 * @dev: PCI device to reset
1471 * @return: 0 if OK, -ENOENT if FLR is not supported by dev
1472 */
1473 int dm_pci_flr(struct udevice *dev);
1474
1475 #define dm_pci_virt_to_bus(dev, addr, flags) \
1476 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), 0, PCI_REGION_TYPE, (flags))
1477 #define dm_pci_bus_to_virt(dev, addr, len, mask, flags, map_flags) \
1478 ({ \
1479 size_t _len = (len); \
1480 phys_addr_t phys_addr = dm_pci_bus_to_phys((dev), (addr), _len, \
1481 (mask), (flags)); \
1482 map_physmem(phys_addr, _len, (map_flags)); \
1483 })
1484
1485 #define dm_pci_phys_to_mem(dev, addr) \
1486 dm_pci_phys_to_bus((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_MEM)
1487 #define dm_pci_mem_to_phys(dev, addr) \
1488 dm_pci_bus_to_phys((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_MEM)
1489 #define dm_pci_phys_to_io(dev, addr) \
1490 dm_pci_phys_to_bus((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_IO)
1491 #define dm_pci_io_to_phys(dev, addr) \
1492 dm_pci_bus_to_phys((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_IO)
1493
1494 #define dm_pci_virt_to_mem(dev, addr) \
1495 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1496 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1497 dm_pci_bus_to_virt((dev), (addr), (len), PCI_REGION_TYPE, \
1498 PCI_REGION_MEM, (map_flags))
1499 #define dm_pci_virt_to_io(dev, addr) \
1500 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
1501 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \
1502 dm_pci_bus_to_virt((dev), (addr), (len), PCI_REGION_TYPE, \
1503 PCI_REGION_IO, (map_flags))
1504
1505 /**
1506 * dm_pci_find_device() - find a device by vendor/device ID
1507 *
1508 * @vendor: Vendor ID
1509 * @device: Device ID
1510 * @index: 0 to find the first match, 1 for second, etc.
1511 * @devp: Returns pointer to the device, if found
1512 * Return: 0 if found, -ve on error
1513 */
1514 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1515 struct udevice **devp);
1516
1517 /**
1518 * dm_pci_find_class() - find a device by class
1519 *
1520 * @find_class: 3-byte (24-bit) class value to find
1521 * @index: 0 to find the first match, 1 for second, etc.
1522 * @devp: Returns pointer to the device, if found
1523 * Return: 0 if found, -ve on error
1524 */
1525 int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
1526
1527 /**
1528 * struct pci_emul_uc_priv - holds info about an emulator device
1529 *
1530 * There is always at most one emulator per client
1531 *
1532 * @client: Client device if any, else NULL
1533 */
1534 struct pci_emul_uc_priv {
1535 struct udevice *client;
1536 };
1537
1538 /**
1539 * struct dm_pci_emul_ops - PCI device emulator operations
1540 */
1541 struct dm_pci_emul_ops {
1542 /**
1543 * read_config() - Read a PCI configuration value
1544 *
1545 * @dev: Emulated device to read from
1546 * @offset: Byte offset within the device's configuration space
1547 * @valuep: Place to put the returned value
1548 * @size: Access size
1549 * @return 0 if OK, -ve on error
1550 */
1551 int (*read_config)(const struct udevice *dev, uint offset,
1552 ulong *valuep, enum pci_size_t size);
1553 /**
1554 * write_config() - Write a PCI configuration value
1555 *
1556 * @dev: Emulated device to write to
1557 * @offset: Byte offset within the device's configuration space
1558 * @value: Value to write
1559 * @size: Access size
1560 * @return 0 if OK, -ve on error
1561 */
1562 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1563 enum pci_size_t size);
1564 /**
1565 * read_io() - Read a PCI I/O value
1566 *
1567 * @dev: Emulated device to read from
1568 * @addr: I/O address to read
1569 * @valuep: Place to put the returned value
1570 * @size: Access size
1571 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1572 * other -ve value on error
1573 */
1574 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1575 enum pci_size_t size);
1576 /**
1577 * write_io() - Write a PCI I/O value
1578 *
1579 * @dev: Emulated device to write from
1580 * @addr: I/O address to write
1581 * @value: Value to write
1582 * @size: Access size
1583 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1584 * other -ve value on error
1585 */
1586 int (*write_io)(struct udevice *dev, unsigned int addr,
1587 ulong value, enum pci_size_t size);
1588 /**
1589 * map_physmem() - Map a device into sandbox memory
1590 *
1591 * @dev: Emulated device to map
1592 * @addr: Memory address, normally corresponding to a PCI BAR.
1593 * The device should have been configured to have a BAR
1594 * at this address.
1595 * @lenp: On entry, the size of the area to map, On exit it is
1596 * updated to the size actually mapped, which may be less
1597 * if the device has less space
1598 * @ptrp: Returns a pointer to the mapped address. The device's
1599 * space can be accessed as @lenp bytes starting here
1600 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1601 * other -ve value on error
1602 */
1603 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1604 unsigned long *lenp, void **ptrp);
1605 /**
1606 * unmap_physmem() - undo a memory mapping
1607 *
1608 * This must be called after map_physmem() to undo the mapping.
1609 * Some devices can use this to check what has been written into
1610 * their mapped memory and perform an operations they require on it.
1611 * In this way, map/unmap can be used as a sort of handshake between
1612 * the emulated device and its users.
1613 *
1614 * @dev: Emuated device to unmap
1615 * @vaddr: Mapped memory address, as passed to map_physmem()
1616 * @len: Size of area mapped, as returned by map_physmem()
1617 * @return 0 if OK, -ve on error
1618 */
1619 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1620 unsigned long len);
1621 };
1622
1623 /* Get access to a PCI device emulator's operations */
1624 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1625
1626 /**
1627 * sandbox_pci_get_emul() - Get the emulation device for a PCI device
1628 *
1629 * Searches for a suitable emulator for the given PCI bus device
1630 *
1631 * @bus: PCI bus to search
1632 * @find_devfn: PCI device and function address (PCI_DEVFN())
1633 * @containerp: Returns container device if found
1634 * @emulp: Returns emulated device if found
1635 * Return: 0 if found, -ENODEV if not found
1636 */
1637 int sandbox_pci_get_emul(const struct udevice *bus, pci_dev_t find_devfn,
1638 struct udevice **containerp, struct udevice **emulp);
1639
1640 /**
1641 * sandbox_pci_get_client() - Find the client for an emulation device
1642 *
1643 * @emul: Emulation device to check
1644 * @devp: Returns the client device emulated by this device
1645 * Return: 0 if OK, -ENOENT if the device has no client yet
1646 */
1647 int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
1648
1649 /**
1650 * board_pci_fixup_dev() - Board callback for PCI device fixups
1651 *
1652 * @bus: PCI bus
1653 * @dev: PCI device
1654 */
1655 extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev);
1656
1657 /**
1658 * PCI_DEVICE - macro used to describe a specific pci device
1659 * @vend: the 16 bit PCI Vendor ID
1660 * @dev: the 16 bit PCI Device ID
1661 *
1662 * This macro is used to create a struct pci_device_id that matches a
1663 * specific device. The subvendor and subdevice fields will be set to
1664 * PCI_ANY_ID.
1665 */
1666 #define PCI_DEVICE(vend, dev) \
1667 .vendor = (vend), .device = (dev), \
1668 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1669
1670 /**
1671 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
1672 * @vend: the 16 bit PCI Vendor ID
1673 * @dev: the 16 bit PCI Device ID
1674 * @subvend: the 16 bit PCI Subvendor ID
1675 * @subdev: the 16 bit PCI Subdevice ID
1676 *
1677 * This macro is used to create a struct pci_device_id that matches a
1678 * specific device with subsystem information.
1679 */
1680 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1681 .vendor = (vend), .device = (dev), \
1682 .subvendor = (subvend), .subdevice = (subdev)
1683
1684 /**
1685 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
1686 * @dev_class: the class, subclass, prog-if triple for this device
1687 * @dev_class_mask: the class mask for this device
1688 *
1689 * This macro is used to create a struct pci_device_id that matches a
1690 * specific PCI class. The vendor, device, subvendor, and subdevice
1691 * fields will be set to PCI_ANY_ID.
1692 */
1693 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1694 .class = (dev_class), .class_mask = (dev_class_mask), \
1695 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1696 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1697
1698 /**
1699 * PCI_VDEVICE - macro used to describe a specific pci device in short form
1700 * @vend: the vendor name
1701 * @dev: the 16 bit PCI Device ID
1702 *
1703 * This macro is used to create a struct pci_device_id that matches a
1704 * specific PCI device. The subvendor, and subdevice fields will be set
1705 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1706 * private data.
1707 */
1708
1709 #define PCI_VDEVICE(vend, dev) \
1710 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1711 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1712
1713 /**
1714 * struct pci_driver_entry - Matches a driver to its pci_device_id list
1715 * @driver: Driver to use
1716 * @match: List of match records for this driver, terminated by {}
1717 */
1718 struct pci_driver_entry {
1719 struct driver *driver;
1720 const struct pci_device_id *match;
1721 };
1722
1723 #define U_BOOT_PCI_DEVICE(__name, __match) \
1724 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1725 .driver = llsym(struct driver, __name, driver), \
1726 .match = __match, \
1727 }
1728
1729 #endif /* __ASSEMBLY__ */
1730 #endif /* _PCI_H */
1731