1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 #ifndef _CPCAP_H_ 3 #define _CPCAP_H_ 4 5 #define CPCAP_VENDOR_ST 0 6 #define CPCAP_VENDOR_TI 1 7 8 #define CPCAP_REVISION_MAJOR(r) (((r) >> 4) + 1) 9 #define CPCAP_REVISION_MINOR(r) ((r) & 0xf) 10 11 #define CPCAP_REVISION_1_0 0x08 12 #define CPCAP_REVISION_1_1 0x09 13 #define CPCAP_REVISION_2_0 0x10 14 #define CPCAP_REVISION_2_1 0x11 15 #define CPCAP_REVISION_3_1 0x19 16 17 /* CPCAP registers */ 18 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */ 19 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */ 20 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */ 21 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */ 22 #define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */ 23 #define CPCAP_REG_INTM2 0x0014 /* Interrupt Mask 2 */ 24 #define CPCAP_REG_INTM3 0x0018 /* Interrupt Mask 3 */ 25 #define CPCAP_REG_INTM4 0x001c /* Interrupt Mask 4 */ 26 #define CPCAP_REG_INTS1 0x0020 /* Interrupt Sense 1 */ 27 #define CPCAP_REG_INTS2 0x0024 /* Interrupt Sense 2 */ 28 #define CPCAP_REG_INTS3 0x0028 /* Interrupt Sense 3 */ 29 #define CPCAP_REG_INTS4 0x002c /* Interrupt Sense 4 */ 30 #define CPCAP_REG_ASSIGN1 0x0030 /* Resource Assignment 1 */ 31 #define CPCAP_REG_ASSIGN2 0x0034 /* Resource Assignment 2 */ 32 #define CPCAP_REG_ASSIGN3 0x0038 /* Resource Assignment 3 */ 33 #define CPCAP_REG_ASSIGN4 0x003c /* Resource Assignment 4 */ 34 #define CPCAP_REG_ASSIGN5 0x0040 /* Resource Assignment 5 */ 35 #define CPCAP_REG_ASSIGN6 0x0044 /* Resource Assignment 6 */ 36 #define CPCAP_REG_VERSC1 0x0048 /* Version Control 1 */ 37 #define CPCAP_REG_VERSC2 0x004c /* Version Control 2 */ 38 39 #define CPCAP_REG_MI1 0x0200 /* Macro Interrupt 1 */ 40 #define CPCAP_REG_MIM1 0x0204 /* Macro Interrupt Mask 1 */ 41 #define CPCAP_REG_MI2 0x0208 /* Macro Interrupt 2 */ 42 #define CPCAP_REG_MIM2 0x020c /* Macro Interrupt Mask 2 */ 43 #define CPCAP_REG_UCC1 0x0210 /* UC Control 1 */ 44 #define CPCAP_REG_UCC2 0x0214 /* UC Control 2 */ 45 46 #define CPCAP_REG_PC1 0x021c /* Power Cut 1 */ 47 #define CPCAP_REG_PC2 0x0220 /* Power Cut 2 */ 48 #define CPCAP_REG_BPEOL 0x0224 /* BP and EOL */ 49 #define CPCAP_REG_PGC 0x0228 /* Power Gate and Control */ 50 #define CPCAP_REG_MT1 0x022c /* Memory Transfer 1 */ 51 #define CPCAP_REG_MT2 0x0230 /* Memory Transfer 2 */ 52 #define CPCAP_REG_MT3 0x0234 /* Memory Transfer 3 */ 53 #define CPCAP_REG_PF 0x0238 /* Print Format */ 54 55 #define CPCAP_REG_SCC 0x0400 /* System Clock Control */ 56 #define CPCAP_REG_SW1 0x0404 /* Stop Watch 1 */ 57 #define CPCAP_REG_SW2 0x0408 /* Stop Watch 2 */ 58 #define CPCAP_REG_UCTM 0x040c /* UC Turbo Mode */ 59 #define CPCAP_REG_TOD1 0x0410 /* Time of Day 1 */ 60 #define CPCAP_REG_TOD2 0x0414 /* Time of Day 2 */ 61 #define CPCAP_REG_TODA1 0x0418 /* Time of Day Alarm 1 */ 62 #define CPCAP_REG_TODA2 0x041c /* Time of Day Alarm 2 */ 63 #define CPCAP_REG_DAY 0x0420 /* Day */ 64 #define CPCAP_REG_DAYA 0x0424 /* Day Alarm */ 65 #define CPCAP_REG_VAL1 0x0428 /* Validity 1 */ 66 #define CPCAP_REG_VAL2 0x042c /* Validity 2 */ 67 68 #define CPCAP_REG_SDVSPLL 0x0600 /* Switcher DVS and PLL */ 69 #define CPCAP_REG_SI2CC1 0x0604 /* Switcher I2C Control 1 */ 70 #define CPCAP_REG_Si2CC2 0x0608 /* Switcher I2C Control 2 */ 71 #define CPCAP_REG_S1C1 0x060c /* Switcher 1 Control 1 */ 72 #define CPCAP_REG_S1C2 0x0610 /* Switcher 1 Control 2 */ 73 #define CPCAP_REG_S2C1 0x0614 /* Switcher 2 Control 1 */ 74 #define CPCAP_REG_S2C2 0x0618 /* Switcher 2 Control 2 */ 75 #define CPCAP_REG_S3C 0x061c /* Switcher 3 Control */ 76 #define CPCAP_REG_S4C1 0x0620 /* Switcher 4 Control 1 */ 77 #define CPCAP_REG_S4C2 0x0624 /* Switcher 4 Control 2 */ 78 #define CPCAP_REG_S5C 0x0628 /* Switcher 5 Control */ 79 #define CPCAP_REG_S6C 0x062c /* Switcher 6 Control */ 80 #define CPCAP_REG_VCAMC 0x0630 /* VCAM Control */ 81 #define CPCAP_REG_VCSIC 0x0634 /* VCSI Control */ 82 #define CPCAP_REG_VDACC 0x0638 /* VDAC Control */ 83 #define CPCAP_REG_VDIGC 0x063c /* VDIG Control */ 84 #define CPCAP_REG_VFUSEC 0x0640 /* VFUSE Control */ 85 #define CPCAP_REG_VHVIOC 0x0644 /* VHVIO Control */ 86 #define CPCAP_REG_VSDIOC 0x0648 /* VSDIO Control */ 87 #define CPCAP_REG_VPLLC 0x064c /* VPLL Control */ 88 #define CPCAP_REG_VRF1C 0x0650 /* VRF1 Control */ 89 #define CPCAP_REG_VRF2C 0x0654 /* VRF2 Control */ 90 #define CPCAP_REG_VRFREFC 0x0658 /* VRFREF Control */ 91 #define CPCAP_REG_VWLAN1C 0x065c /* VWLAN1 Control */ 92 #define CPCAP_REG_VWLAN2C 0x0660 /* VWLAN2 Control */ 93 #define CPCAP_REG_VSIMC 0x0664 /* VSIM Control */ 94 #define CPCAP_REG_VVIBC 0x0668 /* VVIB Control */ 95 #define CPCAP_REG_VUSBC 0x066c /* VUSB Control */ 96 #define CPCAP_REG_VUSBINT1C 0x0670 /* VUSBINT1 Control */ 97 #define CPCAP_REG_VUSBINT2C 0x0674 /* VUSBINT2 Control */ 98 #define CPCAP_REG_URT 0x0678 /* Useroff Regulator Trigger */ 99 #define CPCAP_REG_URM1 0x067c /* Useroff Regulator Mask 1 */ 100 #define CPCAP_REG_URM2 0x0680 /* Useroff Regulator Mask 2 */ 101 102 #define CPCAP_REG_VAUDIOC 0x0800 /* VAUDIO Control */ 103 #define CPCAP_REG_CC 0x0804 /* Codec Control */ 104 #define CPCAP_REG_CDI 0x0808 /* Codec Digital Interface */ 105 #define CPCAP_REG_SDAC 0x080c /* Stereo DAC */ 106 #define CPCAP_REG_SDACDI 0x0810 /* Stereo DAC Digital Interface */ 107 #define CPCAP_REG_TXI 0x0814 /* TX Inputs */ 108 #define CPCAP_REG_TXMP 0x0818 /* TX MIC PGA's */ 109 #define CPCAP_REG_RXOA 0x081c /* RX Output Amplifiers */ 110 #define CPCAP_REG_RXVC 0x0820 /* RX Volume Control */ 111 #define CPCAP_REG_RXCOA 0x0824 /* RX Codec to Output Amps */ 112 #define CPCAP_REG_RXSDOA 0x0828 /* RX Stereo DAC to Output Amps */ 113 #define CPCAP_REG_RXEPOA 0x082c /* RX External PGA to Output Amps */ 114 #define CPCAP_REG_RXLL 0x0830 /* RX Low Latency */ 115 #define CPCAP_REG_A2LA 0x0834 /* A2 Loudspeaker Amplifier */ 116 #define CPCAP_REG_MIPIS1 0x0838 /* MIPI Slimbus 1 */ 117 #define CPCAP_REG_MIPIS2 0x083c /* MIPI Slimbus 2 */ 118 #define CPCAP_REG_MIPIS3 0x0840 /* MIPI Slimbus 3. */ 119 #define CPCAP_REG_LVAB 0x0844 /* LMR Volume and A4 Balanced. */ 120 121 #define CPCAP_REG_CCC1 0x0a00 /* Coulomb Counter Control 1 */ 122 #define CPCAP_REG_CRM 0x0a04 /* Charger and Reverse Mode */ 123 #define CPCAP_REG_CCCC2 0x0a08 /* Coincell and Coulomb Ctr Ctrl 2 */ 124 #define CPCAP_REG_CCS1 0x0a0c /* Coulomb Counter Sample 1 */ 125 #define CPCAP_REG_CCS2 0x0a10 /* Coulomb Counter Sample 2 */ 126 #define CPCAP_REG_CCA1 0x0a14 /* Coulomb Counter Accumulator 1 */ 127 #define CPCAP_REG_CCA2 0x0a18 /* Coulomb Counter Accumulator 2 */ 128 #define CPCAP_REG_CCM 0x0a1c /* Coulomb Counter Mode */ 129 #define CPCAP_REG_CCO 0x0a20 /* Coulomb Counter Offset */ 130 #define CPCAP_REG_CCI 0x0a24 /* Coulomb Counter Integrator */ 131 132 #define CPCAP_REG_ADCC1 0x0c00 /* A/D Converter Configuration 1 */ 133 #define CPCAP_REG_ADCC2 0x0c04 /* A/D Converter Configuration 2 */ 134 #define CPCAP_REG_ADCD0 0x0c08 /* A/D Converter Data 0 */ 135 #define CPCAP_REG_ADCD1 0x0c0c /* A/D Converter Data 1 */ 136 #define CPCAP_REG_ADCD2 0x0c10 /* A/D Converter Data 2 */ 137 #define CPCAP_REG_ADCD3 0x0c14 /* A/D Converter Data 3 */ 138 #define CPCAP_REG_ADCD4 0x0c18 /* A/D Converter Data 4 */ 139 #define CPCAP_REG_ADCD5 0x0c1c /* A/D Converter Data 5 */ 140 #define CPCAP_REG_ADCD6 0x0c20 /* A/D Converter Data 6 */ 141 #define CPCAP_REG_ADCD7 0x0c24 /* A/D Converter Data 7 */ 142 #define CPCAP_REG_ADCAL1 0x0c28 /* A/D Converter Calibration 1 */ 143 #define CPCAP_REG_ADCAL2 0x0c2c /* A/D Converter Calibration 2 */ 144 145 #define CPCAP_REG_USBC1 0x0e00 /* USB Control 1 */ 146 #define CPCAP_REG_USBC2 0x0e04 /* USB Control 2 */ 147 #define CPCAP_REG_USBC3 0x0e08 /* USB Control 3 */ 148 #define CPCAP_REG_UVIDL 0x0e0c /* ULPI Vendor ID Low */ 149 #define CPCAP_REG_UVIDH 0x0e10 /* ULPI Vendor ID High */ 150 #define CPCAP_REG_UPIDL 0x0e14 /* ULPI Product ID Low */ 151 #define CPCAP_REG_UPIDH 0x0e18 /* ULPI Product ID High */ 152 #define CPCAP_REG_UFC1 0x0e1c /* ULPI Function Control 1 */ 153 #define CPCAP_REG_UFC2 0x0e20 /* ULPI Function Control 2 */ 154 #define CPCAP_REG_UFC3 0x0e24 /* ULPI Function Control 3 */ 155 #define CPCAP_REG_UIC1 0x0e28 /* ULPI Interface Control 1 */ 156 #define CPCAP_REG_UIC2 0x0e2c /* ULPI Interface Control 2 */ 157 #define CPCAP_REG_UIC3 0x0e30 /* ULPI Interface Control 3 */ 158 #define CPCAP_REG_USBOTG1 0x0e34 /* USB OTG Control 1 */ 159 #define CPCAP_REG_USBOTG2 0x0e38 /* USB OTG Control 2 */ 160 #define CPCAP_REG_USBOTG3 0x0e3c /* USB OTG Control 3 */ 161 #define CPCAP_REG_UIER1 0x0e40 /* USB Interrupt Enable Rising 1 */ 162 #define CPCAP_REG_UIER2 0x0e44 /* USB Interrupt Enable Rising 2 */ 163 #define CPCAP_REG_UIER3 0x0e48 /* USB Interrupt Enable Rising 3 */ 164 #define CPCAP_REG_UIEF1 0x0e4c /* USB Interrupt Enable Falling 1 */ 165 #define CPCAP_REG_UIEF2 0x0e50 /* USB Interrupt Enable Falling 1 */ 166 #define CPCAP_REG_UIEF3 0x0e54 /* USB Interrupt Enable Falling 1 */ 167 #define CPCAP_REG_UIS 0x0e58 /* USB Interrupt Status */ 168 #define CPCAP_REG_UIL 0x0e5c /* USB Interrupt Latch */ 169 #define CPCAP_REG_USBD 0x0e60 /* USB Debug */ 170 #define CPCAP_REG_SCR1 0x0e64 /* Scratch 1 */ 171 #define CPCAP_REG_SCR2 0x0e68 /* Scratch 2 */ 172 #define CPCAP_REG_SCR3 0x0e6c /* Scratch 3 */ 173 174 #define CPCAP_REG_VMC 0x0eac /* Video Mux Control */ 175 #define CPCAP_REG_OWDC 0x0eb0 /* One Wire Device Control */ 176 #define CPCAP_REG_GPIO0 0x0eb4 /* GPIO 0 Control */ 177 178 #define CPCAP_REG_GPIO1 0x0ebc /* GPIO 1 Control */ 179 180 #define CPCAP_REG_GPIO2 0x0ec4 /* GPIO 2 Control */ 181 182 #define CPCAP_REG_GPIO3 0x0ecc /* GPIO 3 Control */ 183 184 #define CPCAP_REG_GPIO4 0x0ed4 /* GPIO 4 Control */ 185 186 #define CPCAP_REG_GPIO5 0x0edc /* GPIO 5 Control */ 187 188 #define CPCAP_REG_GPIO6 0x0ee4 /* GPIO 6 Control */ 189 190 #define CPCAP_REG_MDLC 0x1000 /* Main Display Lighting Control */ 191 #define CPCAP_REG_KLC 0x1004 /* Keypad Lighting Control */ 192 #define CPCAP_REG_ADLC 0x1008 /* Aux Display Lighting Control */ 193 #define CPCAP_REG_REDC 0x100c /* Red Triode Control */ 194 #define CPCAP_REG_GREENC 0x1010 /* Green Triode Control */ 195 #define CPCAP_REG_BLUEC 0x1014 /* Blue Triode Control */ 196 #define CPCAP_REG_CFC 0x1018 /* Camera Flash Control */ 197 #define CPCAP_REG_ABC 0x101c /* Adaptive Boost Control */ 198 #define CPCAP_REG_BLEDC 0x1020 /* Bluetooth LED Control */ 199 #define CPCAP_REG_CLEDC 0x1024 /* Camera Privacy LED Control */ 200 201 #define CPCAP_REG_OW1C 0x1200 /* One Wire 1 Command */ 202 #define CPCAP_REG_OW1D 0x1204 /* One Wire 1 Data */ 203 #define CPCAP_REG_OW1I 0x1208 /* One Wire 1 Interrupt */ 204 #define CPCAP_REG_OW1IE 0x120c /* One Wire 1 Interrupt Enable */ 205 206 #define CPCAP_REG_OW1 0x1214 /* One Wire 1 Control */ 207 208 #define CPCAP_REG_OW2C 0x1220 /* One Wire 2 Command */ 209 #define CPCAP_REG_OW2D 0x1224 /* One Wire 2 Data */ 210 #define CPCAP_REG_OW2I 0x1228 /* One Wire 2 Interrupt */ 211 #define CPCAP_REG_OW2IE 0x122c /* One Wire 2 Interrupt Enable */ 212 213 #define CPCAP_REG_OW2 0x1234 /* One Wire 2 Control */ 214 215 #define CPCAP_REG_OW3C 0x1240 /* One Wire 3 Command */ 216 #define CPCAP_REG_OW3D 0x1244 /* One Wire 3 Data */ 217 #define CPCAP_REG_OW3I 0x1248 /* One Wire 3 Interrupt */ 218 #define CPCAP_REG_OW3IE 0x124c /* One Wire 3 Interrupt Enable */ 219 220 #define CPCAP_REG_OW3 0x1254 /* One Wire 3 Control */ 221 #define CPCAP_REG_GCAIC 0x1258 /* GCAI Clock Control */ 222 #define CPCAP_REG_GCAIM 0x125c /* GCAI GPIO Mode */ 223 #define CPCAP_REG_LGDIR 0x1260 /* LMR GCAI GPIO Direction */ 224 #define CPCAP_REG_LGPU 0x1264 /* LMR GCAI GPIO Pull-up */ 225 #define CPCAP_REG_LGPIN 0x1268 /* LMR GCAI GPIO Pin */ 226 #define CPCAP_REG_LGMASK 0x126c /* LMR GCAI GPIO Mask */ 227 #define CPCAP_REG_LDEB 0x1270 /* LMR Debounce Settings */ 228 #define CPCAP_REG_LGDET 0x1274 /* LMR GCAI Detach Detect */ 229 #define CPCAP_REG_LMISC 0x1278 /* LMR Misc Bits */ 230 #define CPCAP_REG_LMACE 0x127c /* LMR Mace IC Support */ 231 232 #define CPCAP_REG_TEST 0x7c00 /* Test */ 233 234 #define CPCAP_REG_ST_TEST1 0x7d08 /* ST Test1 */ 235 236 #define CPCAP_REG_ST_TEST2 0x7d18 /* ST Test2 */ 237 238 /* Drivers name */ 239 #define CPCAP_LDO_DRIVER "cpcap_ldo" 240 #define CPCAP_SW_DRIVER "cpcap_sw" 241 242 enum cpcap_regulator_id { 243 CPCAP_SW1, 244 CPCAP_SW2, 245 CPCAP_SW3, 246 CPCAP_SW4, 247 CPCAP_SW5, 248 CPCAP_SW6, 249 CPCAP_VCAM, 250 CPCAP_VCSI, 251 CPCAP_VDAC, 252 CPCAP_VDIG, 253 CPCAP_VFUSE, 254 CPCAP_VHVIO, 255 CPCAP_VSDIO, 256 CPCAP_VPLL, 257 CPCAP_VRF1, 258 CPCAP_VRF2, 259 CPCAP_VRFREF, 260 CPCAP_VWLAN1, 261 CPCAP_VWLAN2, 262 CPCAP_VSIM, 263 CPCAP_VSIMCARD, 264 CPCAP_VVIB, 265 CPCAP_VUSB, 266 CPCAP_VAUDIO, 267 CPCAP_REGULATORS_COUNT, 268 }; 269 270 static const char * const cpcap_regulator_to_name[] = { 271 /* BUCK */ 272 [CPCAP_SW1] = "sw1", 273 [CPCAP_SW2] = "sw2", 274 [CPCAP_SW3] = "sw3", 275 [CPCAP_SW4] = "sw4", 276 [CPCAP_SW5] = "sw5", 277 [CPCAP_SW6] = "sw6", 278 /* LDO */ 279 [CPCAP_VCAM] = "vcam", 280 [CPCAP_VCSI] = "vcsi", 281 [CPCAP_VDAC] = "vdac", 282 [CPCAP_VDIG] = "vdig", 283 [CPCAP_VFUSE] = "vfuse", 284 [CPCAP_VHVIO] = "vhvio", 285 [CPCAP_VSDIO] = "vsdio", 286 [CPCAP_VPLL] = "vpll", 287 [CPCAP_VRF1] = "vrf1", 288 [CPCAP_VRF2] = "vrf2", 289 [CPCAP_VRFREF] = "vrfref", 290 [CPCAP_VWLAN1] = "vwlan1", 291 [CPCAP_VWLAN2] = "vwlan2", 292 [CPCAP_VSIM] = "vsim", 293 [CPCAP_VSIMCARD] = "vsimcard", 294 [CPCAP_VVIB] = "vvib", 295 [CPCAP_VUSB] = "vusb", 296 [CPCAP_VAUDIO] = "vaudio", 297 }; 298 299 static const u32 unknown_val_tbl[] = { 0, }; 300 static const u32 sw1_val_tbl[] = { 750000, 762500, 775000, 787500, 800000, 301 812500, 825000, 837500, 850000, 862500, 302 875000, 887500, 900000, 912500, 925000, 303 937500, 950000, 962500, 975000, 987500, 304 1000000, 1012500, 1025000, 1037500, 305 1050000, 1062500, 1075000, 1087500, 306 1100000, 1112500, 1125000, 1137500, 307 1150000, 1162500, 1175000, 1187500, 308 1200000, 1212500, 1225000, 1237500, 309 1250000, 1262500, 1275000, 1287500, 310 1300000, 1312500, 1325000, 1337500, 311 1350000, 1362500, 1375000, 1387500, 312 1400000, 1412500, 1425000, 1437500, 313 1450000, 1462500, 1475000 }; 314 static const u32 sw2_sw4_val_tbl[] = { 900000, 912500, 925000, 937500, 950000, 315 962500, 975000, 987500, 1000000, 1012500, 316 1025000, 1037500, 1050000, 1062500, 317 1075000, 1087500, 1100000, 1112500, 318 1125000, 1137500, 1150000, 1162500, 319 1175000, 1187500, 1200000, 1212500, 320 1225000, 1237500, 1250000, 1262500, 321 1275000, 1287500, 1300000, 1312500, 322 1325000, 1337500, 1350000, 1362500, 323 1375000, 1387500, 1400000, 1412500, 324 1425000, 1437500, 1450000, 1462500, 325 1475000 }; 326 static const u32 sw3_val_tbl[] = { 1350000, 1800000, 1850000, 1875000 }; 327 static const u32 sw5_val_tbl[] = { 0, 5050000 }; 328 static const u32 vcam_val_tbl[] = { 2600000, 2700000, 2800000, 2900000 }; 329 static const u32 vcsi_val_tbl[] = { 1200000, 1800000 }; 330 static const u32 vdac_val_tbl[] = { 1200000, 1500000, 1800000, 2500000 }; 331 static const u32 vdig_val_tbl[] = { 1200000, 1350000, 1500000, 1875000 }; 332 static const u32 vfuse_val_tbl[] = { 1500000, 1600000, 1700000, 1800000, 1900000, 333 2000000, 2100000, 2200000, 2300000, 2400000, 334 2500000, 2600000, 2700000, 3150000 }; 335 static const u32 vhvio_val_tbl[] = { 2775000 }; 336 static const u32 vsdio_val_tbl[] = { 1500000, 1600000, 1800000, 2600000, 337 2700000, 2800000, 2900000, 3000000 }; 338 static const u32 vpll_val_tbl[] = { 1200000, 1300000, 1400000, 1800000 }; 339 static const u32 vrf1_val_tbl[] = { 2775000, 2500000 }; /* Yes, this is correct */ 340 static const u32 vrf2_val_tbl[] = { 0, 2775000 }; 341 static const u32 vrfref_val_tbl[] = { 2500000, 2775000 }; 342 static const u32 vwlan1_val_tbl[] = { 1800000, 1900000 }; 343 static const u32 vwlan2_val_tbl[] = { 2775000, 3000000, 3300000, 3300000 }; 344 static const u32 vsim_val_tbl[] = { 1800000, 2900000 }; 345 static const u32 vsimcard_val_tbl[] = { 1800000, 2900000 }; 346 static const u32 vvib_val_tbl[] = { 1300000, 1800000, 2000000, 3000000 }; 347 static const u32 vusb_val_tbl[] = { 0, 3300000 }; 348 static const u32 vaudio_val_tbl[] = { 0, 2775000 }; 349 350 struct cpcap_regulator_data { 351 u16 reg; 352 u16 assignment_reg; 353 u16 assignment_mask; 354 u16 mode_mask; 355 u16 volt_mask; 356 u8 volt_shft; 357 u16 mode_val; 358 u16 off_mode_val; 359 u32 val_tbl_sz; 360 const u32 *val_tbl; 361 u32 mode_cntr; 362 u32 volt_trans_time; /* in micro seconds */ 363 u32 turn_on_time; /* in micro seconds */ 364 365 /* 366 * Bit difference between lowest value in val_tbl and start of voltage 367 * table setting in cpcap. Use this for switchers that have many too 368 * many voltages to list in val_tbl. 369 */ 370 u32 bit_offset_from_cpcap_lowest_voltage; 371 }; 372 373 #endif /* _CPCAP_H_ */ 374